11bit or 12 bits ?

Discussion in 'VHDL' started by Amit, May 20, 2007.

  1. Amit

    Amit Guest

    Hello group,

    Can somebody help me with this before I go nuts. I'm thinking of
    writing a VHDL code for uart with parity check. I believe there must
    be 11bits but I visited a website (by chance) that explains it with 12
    bits!!!

    I thought of bit0, ...,bit7 for data (8 bits)
    stop bit and start bits (data frame)
    and one parity check (1 bit)

    total = 11bit

    but this link http://eshop.engineering.uiowa.edu/NI/pdfs/00/97/DS009795.pdf
    explains 12 bit must be there. Why?!!!!!

    thank you
    amit
     
    Amit, May 20, 2007
    #1
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  2. Amit

    Eric Smith Guest

    Amit wrote:
    > I'm thinking of writing a VHDL code for uart with parity check.
    > I believe there must be 11bits

    [...]
    > but this link http://eshop.engineering.uiowa.edu/NI/pdfs/00/97/DS009795.pdf
    > explains 12 bit must be there. Why?!!!!!


    That's a chip that *can* generate parity over 12 bits. It isn't *required*
    to use 12 bits. If you used that chip for computing parity over 8 bits,
    you would tie the other four inputs to logic zero [1].

    Note that for async serial communications as you describe, the start bit
    and stop bit(s) are not part of the parity computation.

    In my experience, the most common async serial modes are:

    8 data bits, no parity, one stop bit (8N1)

    7 data bits, with even parity, one stop bit (7E1)

    7 data bits, with odd parity, one stop bit (7O1)

    In the olden days, electromechanical devices such as Teletypes
    required 1.5 or 2 stop bits, but no modern hardware needs more than one.

    When using 8N1 to transfer 7-bit data, such as ASCII charcters, it is
    common to force the most significant bit to be a zero. That is sometimes
    known (incorrectly) as "space parity" or 7S1. Similarly, but less
    commonly, 8N1 with the MSB force to one is sometimes (incorrectly) known
    as "mark parity" or 7M1. (7M1 is equivalent to 7N2.)

    There's nothing wrong with using eight data bits with parity (8E1 or 8O1),
    if you're sure that the device you're intending to interface to supports
    that. Most devices do not, at least by default.

    Eric


    [1] Or, since there are an even number of unused inputs, they could be tied
    to logic one [2]. It's usually easier just to tie unused inputs to logic
    zero, so that you don't have to think about whether there are an even
    or odd number of them.

    [2] Or, if you tie an odd number of unused inputs to logic one, you can
    swap the even and odd outputs of the chip.
     
    Eric Smith, May 20, 2007
    #2
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  3. In article <>, Amit
    <> wrote:

    > Hello group,
    >
    > Can somebody help me with this before I go nuts. I'm thinking of
    > writing a VHDL code for uart with parity check. I believe there must
    > be 11bits but I visited a website (by chance) that explains it with 12
    > bits!!!
    >
    > I thought of bit0, ...,bit7 for data (8 bits)
    > stop bit and start bits (data frame)
    > and one parity check (1 bit)
    >
    > total = 11bit
    > but this link http://eshop.engineering.uiowa.edu/NI/pdfs/00/97/DS009795.pdf
    > explains 12 bit must be there. Why?!!!!!



    You can have 2 stop bits. (Or even 1.5)
    http://en.wikipedia.org/wiki/UART
    "In mechanical teletypes, the "stop" bit was often stretched to two bit
    times to give the mechanism more time to finish printing a character. A
    stretched "stop" bit also helps resynchronization."

    --
    David M. Palmer (formerly @clark.net, @ematic.com)
     
    David M. Palmer, May 20, 2007
    #3
  4. Amit

    Amit Guest

    On May 19, 9:53 pm, "David M. Palmer" <> wrote:
    > In article <>, Amit
    >
    > <> wrote:
    > > Hello group,

    >
    > > Can somebody help me with this before I go nuts. I'm thinking of
    > > writing a VHDL code for uart with parity check. I believe there must
    > > be 11bits but I visited a website (by chance) that explains it with 12
    > > bits!!!

    >
    > > I thought of bit0, ...,bit7 for data (8 bits)
    > > stop bit and start bits (data frame)
    > > and one parity check (1 bit)

    >
    > > total = 11bit
    > > but this linkhttp://eshop.engineering.uiowa.edu/NI/pdfs/00/97/DS009795.pdf
    > > explains 12 bit must be there. Why?!!!!!

    >
    > You can have 2 stop bits. (Or even 1.5)http://en.wikipedia.org/wiki/UART
    > "In mechanical teletypes, the "stop" bit was often stretched to two bit
    > times to give the mechanism more time to finish printing a character. A
    > stretched "stop" bit also helps resynchronization."
    >
    > --
    > David M. Palmer (formerly @clark.net, @ematic.com)



    Thank you All:

    1) How 1.5 bit is possible? I'm new to digital field and I don't get
    it. How come I must allocate 1.5 bit for a specific purpose?

    2) I was thinking of start-bit and stop-bit as data frame but now you
    are saying that only stop-bit is necessary! how can a receiver must
    know the starting of data then?

    thanks
    amit
     
    Amit, May 20, 2007
    #4
  5. Amit

    Dave Pollum Guest

    On May 20, 2:22 am, Amit <> wrote:
    > On May 19, 9:53 pm, "David M. Palmer" <> wrote:
    >
    >
    >
    > > In article <>, Amit

    >
    > > <> wrote:
    > > > Hello group,

    >
    > > > Can somebody help me with this before I go nuts. I'm thinking of
    > > > writing a VHDL code for uart with parity check. I believe there must
    > > > be 11bits but I visited a website (by chance) that explains it with 12
    > > > bits!!!

    >
    > > > I thought of bit0, ...,bit7 for data (8 bits)
    > > > stop bit and start bits (data frame)
    > > > and one parity check (1 bit)

    >
    > > > total = 11bit
    > > > but this linkhttp://eshop.engineering.uiowa.edu/NI/pdfs/00/97/DS009795.pdf
    > > > explains 12 bit must be there. Why?!!!!!

    >
    > > You can have 2 stop bits. (Or even 1.5)http://en.wikipedia.org/wiki/UART
    > > "In mechanical teletypes, the "stop" bit was often stretched to two bit
    > > times to give the mechanism more time to finish printing a character. A
    > > stretched "stop" bit also helps resynchronization."

    >
    > > --
    > > David M. Palmer (formerly @clark.net, @ematic.com)

    >
    > Thank you All:
    >
    > 1) How 1.5 bit is possible? I'm new to digital field and I don't get
    > it. How come I must allocate 1.5 bit for a specific purpose?
    >
    > 2) I was thinking of start-bit and stop-bit as data frame but now you
    > are saying that only stop-bit is necessary! how can a receiver must
    > know the starting of data then?
    >
    > thanks
    > amit



    Amit;
    ASAIK, 1.5 stop bits is only used for BAUDOT (Teletype), which is 5
    bits per character. I think I just used 2 stop bits for my BAUDOT
    interface.
    HTH
    -Davie Pollum
     
    Dave Pollum, May 20, 2007
    #5
  6. In article <>,
    Amit <> wrote:

    > On May 19, 9:53 pm, "David M. Palmer" <> wrote:
    > > In article <>, Amit
    > >
    > > <> wrote:
    > > > Hello group,

    > >
    > > > Can somebody help me with this before I go nuts. I'm thinking of
    > > > writing a VHDL code for uart with parity check. I believe there must
    > > > be 11bits but I visited a website (by chance) that explains it with 12
    > > > bits!!!

    > >
    > > > I thought of bit0, ...,bit7 for data (8 bits)
    > > > stop bit and start bits (data frame)
    > > > and one parity check (1 bit)

    > >
    > > > total = 11bit
    > > > but this linkhttp://eshop.engineering.uiowa.edu/NI/pdfs/00/97/DS009795.pdf
    > > > explains 12 bit must be there. Why?!!!!!

    > >
    > > You can have 2 stop bits. (Or even 1.5)http://en.wikipedia.org/wiki/UART
    > > "In mechanical teletypes, the "stop" bit was often stretched to two bit
    > > times to give the mechanism more time to finish printing a character. A
    > > stretched "stop" bit also helps resynchronization."
    > >
    > > --
    > > David M. Palmer (formerly @clark.net, @ematic.com)

    >
    >
    > Thank you All:
    >
    > 1) How 1.5 bit is possible? I'm new to digital field and I don't get
    > it. How come I must allocate 1.5 bit for a specific purpose?


    1.5 stop bits just means that the UART will give a '0' signal for at
    least 1.5 bit times between the end of one character (last data or
    parity bit) and the time when the signal goes to '1' for the start bit
    of the next character. For a 300 Baud signal (3.33.. ms bit time) it
    means that the start bit of one character is at least 5 ms after the
    end of the previous.

    It is unlikely to cause problems if you pause for 2 bits when sending a
    character, and only require one bit of pause when receiving a
    character, when 1.5 stop bits have been requested.

    And just because a stop bit exists doesn't mean that you have to store
    it. (Likewise the start bit.)

    > 2) I was thinking of start-bit and stop-bit as data frame but now you
    > are saying that only stop-bit is necessary! how can a receiver must
    > know the starting of data then?


    No, you need a start bit for the reasons you describe. I don't see
    anybody in this thread telling you that you don't need a start bit.


    Other potential gotchas in serial ports:

    Least Significant Bit is transmitted first.

    On reading, you want to sample in the middle of the bit time (n.5
    bit-times after the edge of the start bit going high) for best
    reliability with imperfect clocks.

    The UART typically puts out Vcc (5V, 3.3 V, whatever) for '1' bits and
    0V ground for '0' bits. The level convertor does the inversion to the
    standard, e.g. -5V for '1' and +5V for '0' .

    Some computer serial ports accept 0V for '1' and 5V for '0', so if you
    are never going to plug your circuitry into anything else, you can in
    theory get away with a little bit of protection circuitry and inverters
    in your FPGA. Just don't pretend it is RS-232.

    Level convertors are cheap, small, reliable, provide input protection
    and are easy to use. They include the power inverter to generate the
    negative voltages from your positive supply.

    --
    David M. Palmer (formerly @clark.net, @ematic.com)
     
    David M. Palmer, May 20, 2007
    #6
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