12-bit AdderSubtractor VHDL

Discussion in 'VHDL' started by mugz, Apr 12, 2004.

  1. mugz

    mugz Guest

    I have wrote a 12-bit adder now I need it to subtract now. Here is my
    guidelines:
    ------------------------------------------------------------------------------
    Operation Function Function Code
    ADD Result=A+B 00
    ADDC(add w/carry) Result=A+B+Cin 01
    SUB Result=A+B 10
    SUBB (sub w/borro) Result=A-B-Cin 11

    1. 3-bit full adder: Cout & S2-0 = A 2-0 + B 2-0 + C in
    2. 12-bit full adder: Instantiate 3-bit full adders to generate Cout &
    R = A + B + Cin
    3. 12-bit adder/subtracter: Add a complementer to the B input of the
    12-bit adder, utilizing that and the adder carry input to perform
    addition and subtraction with the single adder.
    -------------------------------------------------------------------------------
    I am on part 3. I got 12 bit adder to work but the function code was
    not needed then. Below is my 12 bit adder and my 12 bit adder/sub
    which will not add cin or subtract right.





    ADDER (Correct)
    -------------------------------------------------------------------------------
    entity adder12 is

    port (A,B : in bit_vector (11 downto 0);
    Cin : in bit;
    Sum : out bit_vector (11 downto 0);
    Cout : out bit);
    end adder12;

    architecture structure of adder12 is component add3bit

    port (A, B : in bit_vector (2 downto 0);
    Cin : in bit;
    Sum : out bit_vector(2 downto 0);
    Cout : out bit);
    end component;

    for all: add3bit use entity work.add3bit (structure);
    signal c0, c1, c2, c3: bit;
    begin

    A0:add3bit port map(A(2 downto 0), B(2 downto 0), Cin, Sum(2
    downto 0), c0);
    A1:add3bit port map(A(5 downto 3), B(5 downto 3), C0, Sum(5
    downto 3), c1);
    A2:add3bit port map(A(8 downto 6), B(8 downto 6), C1, Sum(8
    downto 6), c2);
    A3:add3bit port map(A(11 downto 9), B(11 downto 9), C2, Sum(11
    downto 9), Cout);

    end structure;
    ------------------------------------------------------------------------------





    Adder/Sub (Compiles but wrong)
    --------------------------------------------------------------------------------
    entity addersub12 is

    port (A, B : in bit_vector (11 downto 0);
    F, Cin: in bit;
    Sum: out bit_vector(11 downto 0);
    Cout, Oflow: out bit);
    end addersub12;


    architecture structure of addersub12 is

    component adder12 is
    port (A, B : in bit_vector(11 downto 0);
    Cin : in bit;
    Sum : out bit_vector(11 downto 0);
    Cout : out bit);

    end component;

    for all: adder12 use entity work.adder12 (structure);
    signal IN2: bit_vector(11 downto 0);
    signal tmp: bit_vector(11 downto 0);

    begin
    process(A, B, F)

    begin

    if F = '0' then
    IN2 <= B after 1 ns;
    else
    IN2 <= not B after 1 ns;
    end if;
    end process;

    process (tmp)
    begin
    if A(11) = '0' and IN2(11) = '0' and tmp(11) = '1' then
    Oflow <= '1' after 1 ns;
    elsif A(11) = '1' and IN2(11) = '1' and tmp(11) = '0' then
    Oflow <= '1' after 1 ns;
    else
    Oflow <= '0' after 1 ns;
    end if;
    Sum <= tmp;
    end process ;
    add1: adder12 port map(A, IN2, F, tmp, Cout);
    end structure;
    --------------------------------------------------------------------------------


    Overview: Here is link to assignment
    http://www.eng.auburn.edu/~nelson/courses/elec6200/VHDL Project 1.pdf

    It has already been due but I need to correct for another project. I
    have the first 2 parts done but need to fix the third part.

    I also use the ModlelSim EE to simlulate and compile. It is what we
    are given.

    Any help will be great Thanks.
     
    mugz, Apr 12, 2004
    #1
    1. Advertising

  2. mugz

    Jim Lewis Guest

    You have done B as a ones complement,
    you need a twos complement.

    Twos Complement of B = not B + 1

    Rather than have a 12 bit incrementer, use
    the carry bit to do the +1

    The format of your logic then should be:
    Result = A + BEff + CEff

    You have BEff (In2), you need to correct CEff.
    Also F should be two bits and CEff is a function
    of both bits.

    If you get stuck, first post a truth table of what
    you think CEff should be.

    Cheers,
    Jim
    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


    mugz wrote:

    > I have wrote a 12-bit adder now I need it to subtract now. Here is my
    > guidelines:
    > ------------------------------------------------------------------------------
    > Operation Function Function Code
    > ADD Result=A+B 00
    > ADDC(add w/carry) Result=A+B+Cin 01
    > SUB Result=A+B 10
    > SUBB (sub w/borro) Result=A-B-Cin 11
    >
    > 1. 3-bit full adder: Cout & S2-0 = A 2-0 + B 2-0 + C in
    > 2. 12-bit full adder: Instantiate 3-bit full adders to generate Cout &
    > R = A + B + Cin
    > 3. 12-bit adder/subtracter: Add a complementer to the B input of the
    > 12-bit adder, utilizing that and the adder carry input to perform
    > addition and subtraction with the single adder.
    > -------------------------------------------------------------------------------
    > I am on part 3. I got 12 bit adder to work but the function code was
    > not needed then. Below is my 12 bit adder and my 12 bit adder/sub
    > which will not add cin or subtract right.
    >
    >
    >
    >
    >
    > ADDER (Correct)
    > -------------------------------------------------------------------------------
    > entity adder12 is
    >
    > port (A,B : in bit_vector (11 downto 0);
    > Cin : in bit;
    > Sum : out bit_vector (11 downto 0);
    > Cout : out bit);
    > end adder12;
    >
    > architecture structure of adder12 is component add3bit
    >
    > port (A, B : in bit_vector (2 downto 0);
    > Cin : in bit;
    > Sum : out bit_vector(2 downto 0);
    > Cout : out bit);
    > end component;
    >
    > for all: add3bit use entity work.add3bit (structure);
    > signal c0, c1, c2, c3: bit;
    > begin
    >
    > A0:add3bit port map(A(2 downto 0), B(2 downto 0), Cin, Sum(2
    > downto 0), c0);
    > A1:add3bit port map(A(5 downto 3), B(5 downto 3), C0, Sum(5
    > downto 3), c1);
    > A2:add3bit port map(A(8 downto 6), B(8 downto 6), C1, Sum(8
    > downto 6), c2);
    > A3:add3bit port map(A(11 downto 9), B(11 downto 9), C2, Sum(11
    > downto 9), Cout);
    >
    > end structure;
    > ------------------------------------------------------------------------------
    >
    >
    >
    >
    >
    > Adder/Sub (Compiles but wrong)
    > --------------------------------------------------------------------------------
    > entity addersub12 is
    >
    > port (A, B : in bit_vector (11 downto 0);
    > F, Cin: in bit;
    > Sum: out bit_vector(11 downto 0);
    > Cout, Oflow: out bit);
    > end addersub12;
    >
    >
    > architecture structure of addersub12 is
    >
    > component adder12 is
    > port (A, B : in bit_vector(11 downto 0);
    > Cin : in bit;
    > Sum : out bit_vector(11 downto 0);
    > Cout : out bit);
    >
    > end component;
    >
    > for all: adder12 use entity work.adder12 (structure);
    > signal IN2: bit_vector(11 downto 0);
    > signal tmp: bit_vector(11 downto 0);
    >
    > begin
    > process(A, B, F)
    >
    > begin
    >
    > if F = '0' then
    > IN2 <= B after 1 ns;
    > else
    > IN2 <= not B after 1 ns;
    > end if;
    > end process;
    >
    > process (tmp)
    > begin
    > if A(11) = '0' and IN2(11) = '0' and tmp(11) = '1' then
    > Oflow <= '1' after 1 ns;
    > elsif A(11) = '1' and IN2(11) = '1' and tmp(11) = '0' then
    > Oflow <= '1' after 1 ns;
    > else
    > Oflow <= '0' after 1 ns;
    > end if;
    > Sum <= tmp;
    > end process ;
    > add1: adder12 port map(A, IN2, F, tmp, Cout);
    > end structure;
    > --------------------------------------------------------------------------------
    >
    >
    > Overview: Here is link to assignment
    > http://www.eng.auburn.edu/~nelson/courses/elec6200/VHDL Project 1.pdf
    >
    > It has already been due but I need to correct for another project. I
    > have the first 2 parts done but need to fix the third part.
    >
    > I also use the ModlelSim EE to simlulate and compile. It is what we
    > are given.
    >
    > Any help will be great Thanks.
     
    Jim Lewis, Apr 12, 2004
    #2
    1. Advertising

  3. mugz

    mugz Guest

    Thx Jim. I have not gotten a chance to redo it yet but I understand
    what you are saying. :)


    Jim Lewis <> wrote in message news:<>...
    > You have done B as a ones complement,
    > you need a twos complement.
    >
    > Twos Complement of B = not B + 1
    >
    > Rather than have a 12 bit incrementer, use
    > the carry bit to do the +1
    >
    > The format of your logic then should be:
    > Result = A + BEff + CEff
    >
    > You have BEff (In2), you need to correct CEff.
    > Also F should be two bits and CEff is a function
    > of both bits.
    >
    > If you get stuck, first post a truth table of what
    > you think CEff should be.
    >
    > Cheers,
    > Jim
    > --
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Jim Lewis
    > Director of Training mailto:
    > SynthWorks Design Inc. http://www.SynthWorks.com
    > 1-503-590-4787
    >
    > Expert VHDL Training for Hardware Design and Verification
    > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    >
    >
    > mugz wrote:
    >
    > > I have wrote a 12-bit adder now I need it to subtract now. Here is my
    > > guidelines:
    > > ------------------------------------------------------------------------------
    > > Operation Function Function Code
    > > ADD Result=A+B 00
    > > ADDC(add w/carry) Result=A+B+Cin 01
    > > SUB Result=A+B 10
    > > SUBB (sub w/borro) Result=A-B-Cin 11
    > >
    > > 1. 3-bit full adder: Cout & S2-0 = A 2-0 + B 2-0 + C in
    > > 2. 12-bit full adder: Instantiate 3-bit full adders to generate Cout &
    > > R = A + B + Cin
    > > 3. 12-bit adder/subtracter: Add a complementer to the B input of the
    > > 12-bit adder, utilizing that and the adder carry input to perform
    > > addition and subtraction with the single adder.
    > > -------------------------------------------------------------------------------
    > > I am on part 3. I got 12 bit adder to work but the function code was
    > > not needed then. Below is my 12 bit adder and my 12 bit adder/sub
    > > which will not add cin or subtract right.
    > >
    > >
    > >
    > >
    > >
    > > ADDER (Correct)
    > > -------------------------------------------------------------------------------
    > > entity adder12 is
    > >
    > > port (A,B : in bit_vector (11 downto 0);
    > > Cin : in bit;
    > > Sum : out bit_vector (11 downto 0);
    > > Cout : out bit);
    > > end adder12;
    > >
    > > architecture structure of adder12 is component add3bit
    > >
    > > port (A, B : in bit_vector (2 downto 0);
    > > Cin : in bit;
    > > Sum : out bit_vector(2 downto 0);
    > > Cout : out bit);
    > > end component;
    > >
    > > for all: add3bit use entity work.add3bit (structure);
    > > signal c0, c1, c2, c3: bit;
    > > begin
    > >
    > > A0:add3bit port map(A(2 downto 0), B(2 downto 0), Cin, Sum(2
    > > downto 0), c0);
    > > A1:add3bit port map(A(5 downto 3), B(5 downto 3), C0, Sum(5
    > > downto 3), c1);
    > > A2:add3bit port map(A(8 downto 6), B(8 downto 6), C1, Sum(8
    > > downto 6), c2);
    > > A3:add3bit port map(A(11 downto 9), B(11 downto 9), C2, Sum(11
    > > downto 9), Cout);
    > >
    > > end structure;
    > > ------------------------------------------------------------------------------
    > >
    > >
    > >
    > >
    > >
    > > Adder/Sub (Compiles but wrong)
    > > --------------------------------------------------------------------------------
    > > entity addersub12 is
    > >
    > > port (A, B : in bit_vector (11 downto 0);
    > > F, Cin: in bit;
    > > Sum: out bit_vector(11 downto 0);
    > > Cout, Oflow: out bit);
    > > end addersub12;
    > >
    > >
    > > architecture structure of addersub12 is
    > >
    > > component adder12 is
    > > port (A, B : in bit_vector(11 downto 0);
    > > Cin : in bit;
    > > Sum : out bit_vector(11 downto 0);
    > > Cout : out bit);
    > >
    > > end component;
    > >
    > > for all: adder12 use entity work.adder12 (structure);
    > > signal IN2: bit_vector(11 downto 0);
    > > signal tmp: bit_vector(11 downto 0);
    > >
    > > begin
    > > process(A, B, F)
    > >
    > > begin
    > >
    > > if F = '0' then
    > > IN2 <= B after 1 ns;
    > > else
    > > IN2 <= not B after 1 ns;
    > > end if;
    > > end process;
    > >
    > > process (tmp)
    > > begin
    > > if A(11) = '0' and IN2(11) = '0' and tmp(11) = '1' then
    > > Oflow <= '1' after 1 ns;
    > > elsif A(11) = '1' and IN2(11) = '1' and tmp(11) = '0' then
    > > Oflow <= '1' after 1 ns;
    > > else
    > > Oflow <= '0' after 1 ns;
    > > end if;
    > > Sum <= tmp;
    > > end process ;
    > > add1: adder12 port map(A, IN2, F, tmp, Cout);
    > > end structure;
    > > --------------------------------------------------------------------------------
    > >
    > >
    > > Overview: Here is link to assignment
    > > http://www.eng.auburn.edu/~nelson/courses/elec6200/VHDL Project 1.pdf
    > >
    > > It has already been due but I need to correct for another project. I
    > > have the first 2 parts done but need to fix the third part.
    > >
    > > I also use the ModlelSim EE to simlulate and compile. It is what we
    > > are given.
    > >
    > > Any help will be great Thanks.
     
    mugz, Apr 13, 2004
    #3
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