2 Queries please

Discussion in 'VHDL' started by SarmadEdward, Sep 25, 2008.

  1. SarmadEdward

    SarmadEdward

    Joined:
    Sep 25, 2008
    Messages:
    1
    Hi all
    I am completely new to the VHDL
    I use modelsim SE6.4 revision 2008.06

    I have 2 queries please
    First - When I start simulation of the entity and architecture below - some times the signals my_in1 ,... I see them on the object menu ready to be copied to the waveform and sometimes I dont see them (I am sure that I m doing something wrong sometimes)

    Can you suggest me a test bench (that changes the clock) for the circuit I below?

    Thx

    entity mult_add is
    Port (
    In1: in std_logic_vector(7 downto 0) := "00001100";--to test
    In2: in std_logic_vector(7 downto 0) := "00001100";
    In3: in std_logic_vector(7 downto 0) := "00000001";
    CLK: in std_logic;
    RESULT: out std_logic_vector(15 downto 0)
    );
    end mult_add;
    architecture mydesign of mult_add is

    signal temp: std_logic_vector (15 downto 0) := "0000000000000000";
    constant delay :time := 2 ns;
    signal my_in1, my_in2, my_in3 : std_logic_vector (7 downto 0) := "00000000";

    begin

    mul: process (clk) is
    begin
    if (CLK'event and EN = '1') then
    my_in1 <= In1;
    my_in2 <= In2;
    my_in3 <= In3;
    temp <= my_in1 * my_in2 after 3 ns;
    end if;
    end process mul;
    end architecture mydesign;
    SarmadEdward, Sep 25, 2008
    #1
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