2bit- comparator -- VDHL Error in ModelSim about this Script.

Discussion in 'VHDL' started by quaere1verum@gmail.com, Feb 14, 2014.

  1. Guest

    The error info is not descriptive. Anyone catches it?

    Library ieee;

    Use ieee.std_logic_1164.all;



    -- I am trying to simulate the logic below

    -- aeqb = (a1'.b1').(a0'.b0') + (a1'.b1').(a0.b0) + (a1.b1).(a0'b0') + (a1.b1).(a0.b0)



    Entity two_bit_equal is

    Port (

    a, b: in std_logic_vector(1 downto 0);

    aeqb : out std_logic);

    End two_bit_equal;



    Architecture arch of two_bit_equal is

    Signal p0, p1,p2,p3 : std_logic;

    begin

    aeqb <= (p0 or p1) or (p2 or p3);

    P0 <= (a(1) and b(1)) or (a(0)and b(0));

    P1<= (a(1)and b(1)) and ( (not a(0)) and (not b(0)));

    P2<= ( (not a(1)) and (not b(1))) and (a(0) and b(0));

    P3 <= ( (not a(1)) and (not b(1)) ) and ( (not a(0)) and (not b(0)) );

    End arch;
     
    , Feb 14, 2014
    #1
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  2. Guest

    The test file I am using is this:

    -- ===================================

    Library ieee;

    Use ieee.std_logic_1164.all;



    Entity Test_two_bit_equal is

    End Test_two_bit_equal;



    Architecture arch_test of test_two_bit_equal is



    component two_bit_equal

    Port (

    a, b: in std_logic_vector(1 downto 0);

    aeqb : out std_logic);

    End component;



    Signal p1, p0 : std_logic_vector(1 downto 0);

    Signal pout : std_logic;

    Signal error : std_logic := '0';

    begin

    uut: two_bit_equal port map(a => p0, b => p1, aeqb => pout);

    process

    begin

    p0 <= "00";

    p1 <= "00";

    wait for 1 ns;

    if (pout = '0') then

    error <= '1';

    end if;

    wait for 200 ns;

    p0 <= "01";

    p1 <= "00";

    wait for 1 ns;

    if (pout = '1') then

    error <= '1';

    end if;

    wait for 200 ns;

    p0 <= "01";

    p1 <= "11";

    wait for 1 ns;

    if (pout = '1') then

    error <= '1';

    end if;

    wait for 200 ns;

    p0 <= "11";

    p1 <= "00";

    wait for 1 ns;

    if (pout = '1') then

    error <= '1';

    end if;

    wait for 200 ns;

    p0 <= "11";

    p1 <= "11";

    wait for 1 ns;

    if (pout = '0') then

    error <= '1';

    end if;

    wait for 200 ns;

    p0 <= "10";

    p1 <= "11";

    wait for 1 ns;

    if (pout = '1') then

    error <= '1';

    end if;

    wait for 200 ns;

    p0 <= "10";

    p1 <= "10";

    wait for 1 ns;

    if (pout = '0') then

    error <= '1';

    end if;

    wait for 200 ns;

    p0 <= "11";

    p1 <= "01";

    wait for 1 ns;

    if (pout = '1') then

    error <= '1';

    end if;

    wait for 200 ns;



    if (error = '0') then

    report "No errors detected. Simulation successful" severity failure;

    else

    report "Error detected" severity failure;

    end if;



    end process;

    End arch_test;
     
    , Feb 14, 2014
    #2
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  3. Dio Gratia Guest

    On Friday, February 14, 2014 5:00:42 PM UTC+13, wrote:

    > The error info is not descriptive. Anyone catches it?


    Yes.

    >
    > -- I am trying to simulate the logic below


    P0 P1 P2
    > -- aeqb = (a1'.b1').(a0'.b0') + (a1'.b1').(a0.b0) + (a1.b1).(a0'b0') +

    _

    P3

    > (a1.b1).(a0.b0)


    >
    > P0 <= (a(1) and b(1)) or (a(0)and b(0));



    Should be:

    P0 <= (a(1) and b(1)) and (a(0)and b(0));

    (And ya, I simulated it with your test bench.)

    % ghdl -a two_bit_equal.vhdl
    % ghdl -e Test_two_bit_equal
    david_koontz@Macbook: ghdl -r Test_two_bit_equal --wave=twobit.ghw
    two_bit_equal.vhdl:203:12:mad:1608ns:(report failure): No errors detected. Simulation successful
    ../test_two_bit_equal:error: report failed
    ../test_two_bit_equal:error: simulation failed
    ghdl: compilation error

    (And you could have ended simulation with a wait; statement).
     
    Dio Gratia, Feb 14, 2014
    #3
  4. Guest

    Thank you all, the error was trivial.
    Notice P0 leftmost statement. The error is that it should be AND and not OR
    Correct == (a1.b1).(a0.b0)
    P0 <= (a(1) and b(1)) and (a(0)and b(0));
     
    , Feb 14, 2014
    #4
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