32-Bit Fixed Point Divider Needed

[phuxua...]

Hi all,

Please let me know how to get a 32-Bit Fixed Point Divider, either in
VHDL or Verilog.

The divide.v file shown below does not seem to work, i.e. quotient
stays at '0' and remainder gives incorrect reading regardless of input
values !

Thanks,

Calvin


-------------------------------------------------------------------------------------------------------------------------------------------------------
//
// File divide.v
//
// Unsigned/Signed division based on Patterson and Hennessy's
algorithm.
// Description: Calculates quotient. The "sign" input determines
whether
// signs (two's complement) should be taken into consideration.
//

module divide(
ready,
quotient,
remainder,
dividend,
divider,
sign,
clk
);

input clk;
input sign;
input [31:0] dividend, divider;
output [31:0] quotient, remainder;
output ready;

reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negative_output;

wire [31:0] remainder = (!negative_output) ?
dividend_copy[31:0] :
~dividend_copy[31:0] + 1'b1;

reg [5:0] bit;
wire ready = !bit;

initial bit = 0;
initial negative_output = 0;

always @( posedge clk )

if( ready ) begin

bit = 6'd32;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[31]) ?
{32'd0,dividend} :
{32'd0,~dividend + 1'b1};
divider_copy = (!sign || !divider[31]) ?
{1'b0,divider,31'd0} :
{1'b0,~divider + 1'b1,31'd0};

negative_output = sign &&
((divider[31] && !dividend[31])
||(!divider[31] && dividend[31]));

end
else if ( bit > 0 ) begin

diff = dividend_copy - divider_copy;

quotient_temp = quotient_temp << 1;

if( !diff[63] ) begin

dividend_copy = diff;
quotient_temp[0] = 1'd1;

end

quotient = (!negative_output) ?
quotient_temp :
~quotient_temp + 1'b1;

divider_copy = divider_copy >> 1;
bit = bit - 1'b1;

end
endmodule

 

[Newman]

Hi all,

Please let me know how to get a 32-Bit Fixed Point Divider, either in
VHDL or Verilog.

The divide.v file shown below does not seem to work, i.e. quotient
stays at '0' and remainder gives incorrect reading regardless of input
values !

Thanks,

Calvin

---------------------------------------------------------------------------­---------------------------------------------------------------------------­-
//
// File divide.v
//
// Unsigned/Signed division based on Patterson and Hennessy's
algorithm.
// Description: Calculates quotient. The "sign" input determines
whether
// signs (two's complement) should be taken into consideration.
//

module divide(
ready,
quotient,
remainder,
dividend,
divider,
sign,
clk
);

input clk;
input sign;
input [31:0] dividend, divider;
output [31:0] quotient, remainder;
output ready;

reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negative_output;

wire [31:0] remainder = (!negative_output) ?
dividend_copy[31:0] :
~dividend_copy[31:0] + 1'b1;

reg [5:0] bit;
wire ready = !bit;

initial bit = 0;
initial negative_output = 0;

always @( posedge clk )

if( ready ) begin

bit = 6'd32;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[31]) ?
{32'd0,dividend} :
{32'd0,~dividend + 1'b1};
divider_copy = (!sign || !divider[31]) ?
{1'b0,divider,31'd0} :
{1'b0,~divider + 1'b1,31'd0};

negative_output = sign &&
((divider[31] && !dividend[31])
||(!divider[31] && dividend[31]));

end
else if ( bit > 0 ) begin

diff = dividend_copy - divider_copy;

quotient_temp = quotient_temp << 1;

if( !diff[63] ) begin

dividend_copy = diff;
quotient_temp[0] = 1'd1;

end

quotient = (!negative_output) ?
quotient_temp :
~quotient_temp + 1'b1;

divider_copy = divider_copy >> 1;
bit = bit - 1'b1;

end
endmodule

Calvin,

You might check out the below link for an unsigned serial divider.

It took me a little bit in testbenchland to figure the relationship
between the passed in parameters/inputs and out how to interpret the
results.

The HDL is Verilog.

http://www.opencores.org/projects.cgi/web/serial_div_uu/overview

-Newman

 

[Amal]

Hi all,

Please let me know how to get a 32-Bit Fixed Point Divider, either in
VHDL or Verilog.

The divide.v file shown below does not seem to work, i.e. quotient
stays at '0' and remainder gives incorrect reading regardless of input
values !


---------------------------------------------------------------------------­---------------------------------------------------------------------------­-
//
// File divide.v
//
// Unsigned/Signed division based on Patterson and Hennessy's
algorithm.
// Description: Calculates quotient. The "sign" input determines
whether
// signs (two's complement) should be taken into consideration.
//

module divide(
ready,
quotient,
remainder,
dividend,
divider,
sign,
clk
);

input clk;
input sign;
input [31:0] dividend, divider;
output [31:0] quotient, remainder;
output ready;

reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negative_output;

wire [31:0] remainder = (!negative_output) ?
dividend_copy[31:0] :
~dividend_copy[31:0] + 1'b1;

reg [5:0] bit;
wire ready = !bit;

initial bit = 0;
initial negative_output = 0;

always @( posedge clk )

if( ready ) begin

bit = 6'd32;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[31]) ?
{32'd0,dividend} :
{32'd0,~dividend + 1'b1};
divider_copy = (!sign || !divider[31]) ?
{1'b0,divider,31'd0} :
{1'b0,~divider + 1'b1,31'd0};

negative_output = sign &&
((divider[31] && !dividend[31])
||(!divider[31] && dividend[31]));

end
else if ( bit > 0 ) begin

diff = dividend_copy - divider_copy;

quotient_temp = quotient_temp << 1;

if( !diff[63] ) begin

dividend_copy = diff;
quotient_temp[0] = 1'd1;

end

quotient = (!negative_output) ?
quotient_temp :
~quotient_temp + 1'b1;

divider_copy = divider_copy >> 1;
bit = bit - 1'b1;

end
endmodule

Calvin,

You might check out the below link for an unsigned serial divider.

It took me a little bit in testbenchland to figure the relationship
between the passed in parameters/inputs and out how to interpret the
results.

The HDL is Verilog.

http://www.opencores.org/projects.cgi/web/serial_div_uu/overview

-Newman

Have you checked new numeric_std, fixed and float packages in the neew
ieee_proposed libraray?

http://www.eda.org/vhdl-200x/vhdl-200x-ft/

-- Amal

 

[David Bishop]

Hi all,

Please let me know how to get a 32-Bit Fixed Point Divider, either in
VHDL or Verilog.

The divide.v file shown below does not seem to work, i.e. quotient
stays at '0' and remainder gives incorrect reading regardless of input
values !

You'll find one in the fixed point vhdl packages:
http://www.eda.org/fphdl/

It works by making the number into an integer divider.