3D-Port of natural range <>

Discussion in 'VHDL' started by vollbr0t, Jul 28, 2011.

  1. vollbr0t

    vollbr0t

    Joined:
    Jul 28, 2011
    Messages:
    1
    Hi,

    i would like to create a module (A) with a 3d-array port. To create an array-port i have to use a packge to declare the type of array. I do this like this:

    TYPE test_type is array (natural range <>, natural range <>, natural range <>) of std_logic;

    I have to use "natural range <>" for all three dimensions because the portwidth is depending on generics passed to A:

    entity A is
    generic(
    gen_1 : natural := 5,
    gen_2 : natural := 6,
    gen_3 : natural := 7);
    port(
    matrix : IN test_type(gen_1 downto 0, gen_2 downto 0, gen_3 downto 0) );

    The simulation works fine with this, but in synthesis i get "Matrix not supported yet" on the 3D-Port-Line.

    Because of the required "natural range <>" i can not use subtype for the declaration in the package, and passing the generics to the package to not use natural range is not possible.

    Do you have any idea of getting this to syenthesis?

    Best regards,
    Jan
     
    vollbr0t, Jul 28, 2011
    #1
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