8 bit into 256 bit shift register

Discussion in 'VHDL' started by Christian Vallant, May 23, 2006.

  1. Hello!

    I have an 8 bit data-bus and want to load a 256 bit-shift-register with
    it. So i will load the 8 bits into the shift-register and shift 8 times
    left the register and the i load the next 8 bits from the databus and so
    on.
    The problem is, that i'am a beginner in vhdl and don't know, how to load
    only 8 bits in the register. I
    Can onyone help me to find a solution for this problem. I need the
    vhdl-code, to load the 8 bits into the 265 bit register.

    Best regards
    Christian
     
    Christian Vallant, May 23, 2006
    #1
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  2. Christian Vallant

    Guest

    Hi,
    you can select part of a register by specifing a range to write to.

    for example:
    reg256(7 downto 0) <= reg8;

    This will select the 8 lowest bits of the 256-bit register reg256 and
    set them to the value of the 8-bit register reg8.

    /Åke Forslund
     
    , May 23, 2006
    #2
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  3. Christian Vallant a écrit :
    > Hello!
    >
    > I have an 8 bit data-bus and want to load a 256 bit-shift-register with
    > it. So i will load the 8 bits into the shift-register and shift 8 times
    > left the register and the i load the next 8 bits from the databus and so
    > on.
    > The problem is, that i'am a beginner in vhdl and don't know, how to load
    > only 8 bits in the register. I
    > Can onyone help me to find a solution for this problem. I need the
    > vhdl-code, to load the 8 bits into the 265 bit register.
    >
    > Best regards
    > Christian


    Hello,

    In complement to the answer from Åke Forslund, only for another view: do
    you really need a bit shifter, or a 8 levels stack ?

    Pascal
     
    Pascal Peyremorte, May 23, 2006
    #3
  4. Pascal Peyremorte wrote:
    > Christian Vallant a écrit :
    >
    >> Hello!
    >>
    >> I have an 8 bit data-bus and want to load a 256 bit-shift-register
    >> with it. So i will load the 8 bits into the shift-register and shift 8
    >> times left the register and the i load the next 8 bits from the
    >> databus and so on.
    >> The problem is, that i'am a beginner in vhdl and don't know, how to
    >> load only 8 bits in the register. I
    >> Can onyone help me to find a solution for this problem. I need the
    >> vhdl-code, to load the 8 bits into the 265 bit register.
    >>
    >> Best regards
    >> Christian

    >
    >
    > Hello,
    >
    > In complement to the answer from Åke Forslund, only for another view: do
    > you really need a bit shifter, or a 8 levels stack ?
    >
    > Pascal


    I want to store 256 data bits into a 256 Bit shift register. This data
    will later be used for further computations. Here is my current, not
    working, code:


    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.numeric_std.all;

    entity phelix_interface is
    generic (n :integer := 256);
    port (data_in: in std_logic_vector(n-1 downto 0);
    data_out: out std_logic_vector(n-1 downto 0);
    key_load: in std_logic;
    clk: in std_logic);
    end phelix_interface;

    -------------------------------------------------------------------

    architecture structure of phelix_interface is
    signal tmp_data: std_logic_vector(255 downto 0);

    component SHIFT_REG256
    port(CLK, SLOAD : in std_logic;
    D : in std_logic_vector(255 downto 0);
    Q : out std_logic_vector(255 downto 0));
    end component;

    begin
    DUTSHIFT : SHIFT_REG256
    port map(CLK => clk,
    SLOAD => key_load,
    D => tmp_data,
    Q => data_out);

    test: process(key_load)
    begin
    if (clk'event and clk='1') then
    tmp_data(7 downto 0) <= data_in;
    data_out <= tmp_data;
    end if;
    end process test;

    end structure;


    The shift register is a rotate left register. The shift register can be
    read out parallel. Maybe anyone can complete the code for my requirements.

    lg chis
     
    Christian Vallant, May 23, 2006
    #4
  5. Christian Vallant wrote:


    > use ieee.std_logic_unsigned.all;


    Remove this. This is not a standard library - you don't need it.


    > entity phelix_interface is
    > generic (n :integer := 256);
    > port (data_in: in std_logic_vector(n-1 downto 0);
    > data_out: out std_logic_vector(n-1 downto 0);
    > key_load: in std_logic;
    > clk: in std_logic);
    > end phelix_interface;


    Are you sure, that data_in has the same bitwidth as data_out? You were
    talking about receiving 8 bits and shifting it into a 256 bit register.


    > component SHIFT_REG256
    > port(CLK, SLOAD : in std_logic;
    > D : in std_logic_vector(255 downto 0);
    > Q : out std_logic_vector(255 downto 0));
    > end component;


    Whats the purpose of this component?



    > test: process(key_load)
    > begin
    > if (clk'event and clk='1') then
    > tmp_data(7 downto 0) <= data_in;
    > data_out <= tmp_data;
    > end if;
    > end process test;


    You process sensitivity list is completely wrong: key_load never not
    evaluated in this process - but clk is!



    > The shift register is a rotate left register.


    Pardon? What? You want to shift 8 bits into the register and shift all
    other 8-bit-words. Do you really need the bits, that will be shifted
    out? Why and how do you want to feed them into the shift register?

    -> Take a pen and a paper - or if you are a geek, take something like
    xfig ;-). Make a drawing. Make your ideas become more clear!



    The following piece of code may be an idea how to implement something,
    that _may_ be similar, what you want (I can only guess). I am certain,
    that this fits not exactly, but it may give you some ideas.

    signal data_in : std_ulogic_vector(7 downto 0);
    signal reset,clk : std_ulogic;
    signal shiftreg : std_ulogic_vector(255 downto 0);

    process(reset,clk)
    begin
    if (reset='1') then
    shiftreg<=(others=>'0');
    elsif rising_edge(clk) then
    for N in 0 to 30 loop
    shiftreg((N+1)*8+7 downto (N+1)*8)<=shiftreg(N*8+7 downto N*8);
    end loop;
    shiftreg(7 downto 0)<=data_in;
    end if;
    end process;

    Ralf
     
    Ralf Hildebrandt, May 23, 2006
    #5
  6. Hi,

    How can I make the statement "key_data <= din(7 downto 0) & key_data(0
    to 247);" working in the following code:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity load is
    port(din: in std_logic_vector(7 downto 0);
    clk, key_load: in std_logic;
    key_out: out std_logic_vector(0 to 255));
    end load;

    architecture behav of load is
    signal key_data: std_logic_vector(0 to 255);
    signal key_data_tmp: std_logic_vector(0 to 255);
    begin
    default: process(clk)
    begin
    key_out <= (others => '0');
    key_data <= (others => '0');
    key_data <= din(7 downto 0) & key_data(0 to 247);
    key_out <= key_data;
    end process default;
    end behav;

    regards bernie
     
    Bernhard Knauder, May 23, 2006
    #6
  7. Hi,

    How can I make the statement "key_data <= din(7 downto 0) & key_data(0
    to 247);" working in the following code:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity load is
    port(din: in std_logic_vector(7 downto 0);
    clk, key_load: in std_logic;
    key_out: out std_logic_vector(0 to 255));
    end load;

    architecture behav of load is
    signal key_data: std_logic_vector(0 to 255);
    signal key_data: std_logic_vector(0 to 255);
    begin
    default: process(clk)
    begin
    key_out <= (others => '0');
    key_data <= (others => '0');
    key_data <= din(7 downto 0) & key_data(0 to 247);
    key_out <= key_data;
    end process default;
    end behav;

    regards bernie
     
    Bernhard Knauder, May 23, 2006
    #7
  8. Hi,

    How can I make the statement "key_data <= din(7 downto 0) & key_data(0
    to 247);" working in the following code:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity load is
    port(din: in std_logic_vector(7 downto 0);
    clk, key_load: in std_logic;
    key_out: out std_logic_vector(0 to 255));
    end load;

    architecture behav of load is
    signal key_data: std_logic_vector(0 to 255);
    begin
    default: process(clk)
    begin
    key_out <= (others => '0');
    key_data <= (others => '0');
    key_data <= din(7 downto 0) & key_data(0 to 247);
    key_out <= key_data;
    end process default;
    end behav;

    regards bernie
     
    Bernhard Knauder, May 23, 2006
    #8
  9. Bernhard Knauder wrote:

    > How can I make the statement "key_data <= din(7 downto 0) & key_data(0
    > to 247);" working in the following code:


    Has to be 0 to 7.
    -- Mike Treseler

    _______________________________________
    library ieee;
    use ieee.std_logic_1164.all;

    entity load is
    port(din : in std_logic_vector(0 to 7);
    rst, clk : in std_logic;
    key_out : out std_logic_vector(0 to 255));
    end load;
    architecture synth of load is
    begin
    one : process(rst, clk) is
    subtype long_vec is std_logic_vector(key_out'range);
    subtype short_vec is std_logic_vector(din'range);
    subtype mid_vec is
    std_logic_vector(0 to long_vec'length - short_vec'length-1);
    variable key_data_v : long_vec;
    constant init_data : long_vec := (others => '0');
    begin
    if rst = '1' then
    key_data_v := init_data;
    elsif rising_edge(clk) then
    key_data_v := din & key_data_v(mid_vec'range);
    end if;
    key_out <= key_data_v;
    end process one;
    end synth;
     
    Mike Treseler, May 24, 2006
    #9
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