8-bit to 32-bit expansion

Discussion in 'VHDL' started by Vagant, Oct 24, 2007.

  1. Vagant

    Vagant Guest

    Hello All,

    I am interested how to design interface between parallel port of PC
    and FPGA-based device which has to have 16-bit data bus and 16-bit
    address bus. Thus, I have a problem how to expand 8 data lines of a
    parallel
    port into 32 bit bus. How such interface can be described in VHDL?
    Vagant, Oct 24, 2007
    #1
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  2. Vagant a écrit :
    > Hello All,
    >
    > I am interested how to design interface between parallel port of PC
    > and FPGA-based device which has to have 16-bit data bus and 16-bit
    > address bus. Thus, I have a problem how to expand 8 data lines of a
    > parallel
    > port into 32 bit bus. How such interface can be described in VHDL?
    >

    Is it a school exercice ?
    Let you to use 4 latches selected by 2 adresses lines
    Pascal Peyremorte, Oct 24, 2007
    #2
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  3. Vagant

    Vagant Guest

    On Oct 24, 10:13 am, Pascal Peyremorte
    <> wrote:
    > Vagant a écrit :> Hello All,
    >
    > > I am interested how to design interface between parallel port of PC
    > > and FPGA-based device which has to have 16-bit data bus and 16-bit
    > > address bus. Thus, I have a problem how to expand 8 data lines of a
    > > parallel
    > > port into 32 bit bus. How such interface can be described in VHDL?

    >
    > Is it a school exercice ?
    > Let you to use 4 latches selected by 2 adresses lines


    It is not a school exercise. Using 4 latches with 2 address lines
    doesn't make much sense to me until it explained in detail. How you
    propose to connect them
    in order to achieve building a 32-bit bus as an output?
    Vagant, Oct 26, 2007
    #3
  4. Vagant schrieb:

    > I am interested how to design interface between parallel port of PC
    > and FPGA-based device which has to have 16-bit data bus and 16-bit
    > address bus.


    => You need a Port Control Component, that handles bus communication via
    the parallel port.
    => You need a state machine or CPU that is connected to this Port
    Control Component and that does something with the transmitted data.


    > How such interface can be described in VHDL?


    Read the documentation of commercial IP cores how they can be interfaced
    to state machines / CPUs to have an idea, what job the Port Control
    Component has to do.

    Often such peripheral components are connected using an asynchronous RAM
    interface. (address bus, data bus (in and out), chip select, write enable)

    Ralf
    Ralf Hildebrandt, Oct 26, 2007
    #4
  5. Vagant

    Vagant Guest

    On Oct 26, 3:36 pm, Ralf Hildebrandt <> wrote:
    > Vagant schrieb:
    >
    > > I am interested how to design interface between parallel port of PC
    > > and FPGA-based device which has to have 16-bit data bus and 16-bit
    > > address bus.

    >
    > => You need a Port Control Component, that handles bus communication via
    > the parallel port.
    > => You need a state machine or CPU that is connected to this Port
    > Control Component and that does something with the transmitted data.
    >
    > Ralf


    Thank you.
    Has this Port Control Component to be a separate PCB or it can be FPGA-
    based?
    Vagant, Oct 26, 2007
    #5
  6. Vagant schrieb:


    > Has this Port Control Component to be a separate PCB or it can be FPGA-
    > based?


    As you wish. Usually such a component is used as a subcomponent inside a
    bigger design inside the FPGA.


    For beginners I recommend to simulate, simulate, simulate and then
    finally take an FPGA. Chose a small and easy example.

    Ralf
    Ralf Hildebrandt, Oct 26, 2007
    #6
  7. Vagant

    Vagant Guest

    On Oct 26, 7:54 pm, Ralf Hildebrandt <> wrote:
    > Vagant schrieb:
    >
    > > Has this Port Control Component to be a separate PCB or it can be FPGA-
    > > based?

    >
    > As you wish. Usually such a component is used as a subcomponent inside a
    > bigger design inside the FPGA.
    >
    > For beginners I recommend to simulate, simulate, simulate and then
    > finally take an FPGA. Chose a small and easy example.
    >
    > Ralf


    Yes, I am struggling with this..but hope my simple design will get
    working one day! :) The most difficult thing is to get the key concept
    about such 8-bit->32-bit expansion. At the moment I still have not
    understood that. But I've no new question anyway.. I will just reflect
    on whole situation for a while and try to make my simple design
    working.
    Vagant, Oct 27, 2007
    #7
  8. Vagant schrieb:

    > The most difficult thing is to get the key concept
    > about such 8-bit->32-bit expansion.


    No, this is not your problem. Vector width expansion is easy:

    use IEEE.Numeric_std.all;

    signal vec32 : std_ulogic_vector(31 downto 0);
    signal vec8 : std_ulogic_vector(7 downto 0);

    vec32<=std_ulogic_vector(resize(unsigned(vec8),vec32'length));
    -- or
    vec32<=std_ulogic_vector(resize( signed(vec8),vec32'length));


    Your problem is (1) data transfer from the FPGA to the PC and (2) access
    of the transferred data inside the FPGA.


    Ralf
    Ralf Hildebrandt, Oct 28, 2007
    #8
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