8bit Shift Add Multiplication Algorithm in VHDL: not synthesizing

Discussion in 'VHDL' started by apakhira, Oct 17, 2011.

  1. apakhira

    apakhira

    Joined:
    Oct 17, 2011
    Messages:
    2
    Hi.
    Here's my code for an 8bit Shift and Add Multiplier in VHDL. Thing is it is running perfectly in pre-synthesis behavioral simulation, but does not work in post-synthesis simulation.
    Code:
    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.std_logic_arith.all;
    use IEEE.std_logic_unsigned.all;
    
    ENTITY mult IS
    PORT ( a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
           b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
           start: IN STD_LOGIC;
           clk: IN STD_LOGIC;
           rst: IN STD_LOGIC;
           
           busy: OUT STD_LOGIC; 
           prod: OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
    END ENTITY mult;
    
    ARCHITECTURE behav OF mult IS
    TYPE state is (IDLE,COUNT);
    SIGNAL pres, nxt: state;
    SIGNAL a_tmp, b_tmp, tmp: STD_LOGIC_VECTOR(15 DOWNTO 0);
    BEGIN
    
    --Memory
    PROCESS(rst,clk)
    BEGIN
        IF RST='1' THEN
        pres<=idle;
        
        
        ELSIF(clk'event and clk='1') THEN
        pres<=nxt;
        END IF;
    END PROCESS;
    
    -- Next State Logic
    PROCESS(pres,clk)
    VARIABLE cnt: INTEGER RANGE 0 TO 25;
    BEGIN
        CASE pres IS 
            WHEN IDLE =>
                
                cnt:=0;
                tmp<="0000000000000000";
                IF start='1' THEN 
                a_tmp<="00000000"&a;
       			b_tmp<="00000000"&b;
        		nxt<= COUNT;
                ELSE nxt <= IDLE;
                END IF;
            
            WHEN COUNT =>
                if(clk='1') then
                busy<='1';
                
                
                cnt:=cnt+1;
                
                IF b_tmp(0)='1' THEN tmp<=tmp+a_tmp;
                END IF;
                a_tmp<=(a_tmp(14 DOWNTO 0))&'0';    -- Left Shift
                b_tmp<=b_tmp(0)&(b_tmp(15 DOWNTO 1));   --Right Shift
                if(cnt>=8) then 
                nxt<=IDLE;
                busy<='0';
                prod<=tmp;
    
                else nxt<=COUNT;
                end if;
                end if;
                
    
         END CASE;
    
    END PROCESS;
    
    
    END ARCHITECTURE;
    
    What's the problem here?

    Thanks
    apakhira, Oct 17, 2011
    #1
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  2. apakhira

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    The problem seems to be the clock signal.
    Replace (clk='1') with Rising_edge(clk), hopefully will this solve some of your problems.
    Your welcome
    jeppe, Oct 17, 2011
    #2
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  3. apakhira

    apakhira

    Joined:
    Oct 17, 2011
    Messages:
    2
    Nope, that didn't work.
    In any case, if I did put a rising-edge detector there, wouldn't it be odd? Withing the Next State Combinational Logic?

    Now what can I try?
    apakhira, Oct 18, 2011
    #3
  4. apakhira

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Well - you got another problem ...namely

    By using signals and <= assigment must you be aware the fact that signals
    will not get their values before the process ends.

    Please search the net for the free interactive book: Evita VHDL
    In chapter 6 will you learn about processes and the difference between variables and signals.

    Perhaps could your problems be solved by changing all "internal" storage to variables.

    ...
    Last edited: Oct 18, 2011
    jeppe, Oct 18, 2011
    #4
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