a crazy problem

Discussion in 'VHDL' started by Rock Lee, Jun 29, 2007.

  1. Rock Lee

    Rock Lee

    Joined:
    Jun 29, 2007
    Messages:
    1
    Hello
    I'm a begginer in VHDL
    I want to describe 74193 with the VHDL but I fail
    the code is:
    library ieee;
    use ieee.std_logic_1164.all;
    USE ieee.Std_logic_unsigned.all;

    entity counter is
    port (
    aftellen : in std_logic; -- kloksignaal aftellen
    optellen : in std_logic; -- kloksignaal optellen
    clear : in std_logic; -- clear
    enable : in std_logic; -- enable signaal
    load : in std_logic; -- load
    data_in : in std_logic_vector(3 downto 0); -- data ingangen
    data_out : out std_logic_vector(3 downto 0); -- telleruitgangen
    carry_out : out std_logic -- carry out
    );
    end counter ;

    architecture gedrag of counter is
    signal uit : std_logic_vector(3 downto 0); --signaal variable (buffer)
    begin
    process(optellen,aftellen,clear,load)
    begin
    if (optellen'event and optellen = '1')then --event driven (als de flank omlaag gaat)
    if(clear = '0')then
    if (uit = "1111") then --als op max. komt dan
    uit <= (others =>'0'); --teller op min. zetten
    else
    uit <= uit + 1; -- optellen --anders optellen
    end if;
    end if;
    elsif (aftellen'event and aftellen = '1') then --event driven
    if(clear = '0')then
    if (uit = "0000") then --als teller op min. komt
    uit <= "1111"; --teller op max. zetten
    else
    uit <= uit - 1; -- aftellen --anders aftellen
    end if;
    end if;
    elsif (clear = '1') then --als clear hoog is
    uit <= (others =>'0'); --clear buffer
    elsif (load'event and load = '1') then --event driven (werkt niet in simulatie) als load laag wordt
    if(clear = '0')then
    data_out <= data_in after 2 ns; --data_out wordt data_in
    end if;
    end if;
    data_out <= uit; --zet buffer in data_out
    end process;
    end gedrag;
    6 errors at the same line(red)said: can't infer register for signal"uint[3]"because signal dose not hold its value outside clock edge
    Can anyone help me?
    Thanks!
     
    Rock Lee, Jun 29, 2007
    #1
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