A difference between VHDL sources working

Discussion in 'VHDL' started by toomuch, Dec 29, 2003.

  1. toomuch

    toomuch Guest

    Hi

    Can someone tell me if there is a defference between the following two VHDL
    sources working:
    1.
    process

    begin

    wait until C'event and C='1';

    if B='0' then

    Q<=B;

    else

    Q<= A;

    end if;

    end process;



    2.

    process

    begin

    if B='0' then

    wait until C'event and C='1';

    Q<=B;

    else

    wait until C'event and C='1';

    Q<=A;

    end if;

    end process;


    Simulation of this two processes gives different results. Does anybody know
    why? Is there a specification discussing those cases?

    Thanks for any help
     
    toomuch, Dec 29, 2003
    #1
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  2. toomuch

    Marcin Guest

    Hi,

    1. You wait for rising edge on C, then sample the B signal and decide
    whether to assign A or B to Q.
    2. The value of B is examined at the beginning of process execution
    and you choose one of the if-else branch immediately. After that you
    only wait for rising edge on C to assign a value to Q.


    The first will synthesize to simple flip-flop with synchronous reset
    the second will synthesize to something more complex which probably is
    not what you want.

    Marcin

    "toomuch" <> wrote in message news:<bsq239$sba$>...
    > Hi
    >
    > Can someone tell me if there is a defference between the following two VHDL
    > sources working:
    > 1.
    > process
    >
    > begin
    >
    > wait until C'event and C='1';
    >
    > if B='0' then
    >
    > Q<=B;
    >
    > else
    >
    > Q<= A;
    >
    > end if;
    >
    > end process;
    >
    >
    >
    > 2.
    >
    > process
    >
    > begin
    >
    > if B='0' then
    >
    > wait until C'event and C='1';
    >
    > Q<=B;
    >
    > else
    >
    > wait until C'event and C='1';
    >
    > Q<=A;
    >
    > end if;
    >
    > end process;
    >
    >
    > Simulation of this two processes gives different results. Does anybody know
    > why? Is there a specification discussing those cases?
    >
    > Thanks for any help
     
    Marcin, Dec 30, 2003
    #2
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