Hi guys, I'm quite new to VHDL and Verilog. I would like to ask a few simple questions.
1) I read from some internet sources stating that 'file' is an object class. Is it correct? If it is, what is it for and how do we use it?(in general)
2) If I have two architectures in my design, I only need to declare my packages, libraries and entity once right?
3) If I declared a package, which contains say, Q=2. In my design I have 2 architectures. In the first one, I assigned 1 to Q. My question is will this changing of Q's value affect the second architecture? If I were to use Q in the second arch, what will the value be??
4) What is the used of 'generic' in vhdl? I've read somewhere that 'parameter' in verilog does almost the same thing. Can anyone elaborate on this??
Thank you very much!
1) I read from some internet sources stating that 'file' is an object class. Is it correct? If it is, what is it for and how do we use it?(in general)
2) If I have two architectures in my design, I only need to declare my packages, libraries and entity once right?
3) If I declared a package, which contains say, Q=2. In my design I have 2 architectures. In the first one, I assigned 1 to Q. My question is will this changing of Q's value affect the second architecture? If I were to use Q in the second arch, what will the value be??
4) What is the used of 'generic' in vhdl? I've read somewhere that 'parameter' in verilog does almost the same thing. Can anyone elaborate on this??
Thank you very much!