A good solution wanted...

[48 bytes]

I'm having this little trouble with this structural instantiation of
some component (you can figure as soon as you see the code sample...
Yeah, a processor's datapath). I'm using Xilinx ISE 8.2i and I'm
working on a Spartan 3 XC3S200.

Here is my VHDL code, code that gets thru the syntesize process
perfectly and that I assume to simulate in either ISE Sim or
ModelSim...

entity first is
Port ( i_clk : in STD_LOGIC;
i_rst : in STD_LOGIC;
o_result : out STD_LOGIC_VECTOR(31 downto 0));
end first;

architecture Structural of first is
component Datapath1 is
Port ( i_rst : in std_logic;
i_clk : in std_logic;
o_data : out std_logic_vector(31 downto 0));
end component;
[there are some component declarations here]

signal readadd1, readadd2 : std_logic_vector (4 downto 0);
signal writadd : std_logic_vector (4 downto 0);
signal operins : std_logic_vector (5 downto 0);
[there are some signals here]
begin
datapath: Datapath1 port map (i_rst => i_rst, i_clk => i_clk, o_data(31
downto 26) => open,
o_data(25 downto 21) => readadd1, o_data(20 downto 16) => readadd2,
o_data(15 downto 11) => writadd, o_data(10 downto 6) => open,
o_data(5 downto 0) => operins);
[more code continues ...]

But unfortunately, well, according to LRM 4.3.2.2, "Actual OPEN for a
formal o_data that is associated individually is illegal". Is there a
way to be able to fix this code and finally get simulate this stuff
(Neither ModelSim XE or ISE Simulator wants to accept this code)? What
approach should I use instead of leaving some of the o_data pins of
datapath unconnected?

Thanks beforehand for your answers,

Juan Pablo Garcia,
also known as 48 bytes.

 

[Brian Drummond]

I'm having this little trouble with this structural instantiation of
some component (you can figure as soon as you see the code sample...
Yeah, a processor's datapath). I'm using Xilinx ISE 8.2i and I'm
working on a Spartan 3 XC3S200.

architecture Structural of first is
component Datapath1 is
Port ( i_rst : in std_logic;
i_clk : in std_logic;
o_data : out std_logic_vector(31 downto 0));
end component;
[there are some component declarations here]

datapath: Datapath1 port map (i_rst => i_rst, i_clk => i_clk, o_data(31
downto 26) => open,
o_data(25 downto 21) => readadd1, o_data(20 downto 16) => readadd2,
o_data(15 downto 11) => writadd, o_data(10 downto 6) => open,
o_data(5 downto 0) => operins);

But unfortunately, well, according to LRM 4.3.2.2, "Actual OPEN for a
formal o_data that is associated individually is illegal".

Associate o_data with a new 32 bit internal signal; you can connect
subranges of this signal to readadd1, readadd2 etc.

Unused subranges will be optimised out during synthesis.

- Brian