a little C code to VHDL

Discussion in 'VHDL' started by Loppy, May 19, 2006.

  1. Loppy

    Loppy Guest

    Hi,

    I need translate the C code:

    int incrementarmodL(int input,int mod)
    {
    int salida;

    salida = (input+2)%mod;
    return salida;
    }

    To VHDL but I Can´t translate because I don´t understand very well
    the REM operation in VHDL.

    The VHDL code that I am triying :

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    --use IEEE.NUMERIC_STD.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    --use IEEE.STD_LOGIC_UNSIGNED.ALL;



    entity incmodL is
    generic ( constant paso: std_logic_vector(7 downto 0):="00000010";
    constant cero: std_logic_vector(7 downto 0):="00000000"
    );

    port ( entrada : in std_logic_vector(7 downto 0);
    modulo : in std_logic_vector(7 downto 0);
    reset : in std_logic;
    salida : inout std_logic_vector(7 downto 0)
    );
    end incmodL;

    architecture comportamiento of incmodL is
    signal tmp : std_logic_vector(7 downto 0):="00000000";

    begin

    process(entrada,modulo,reset)
    begin
    if reset='1' then
    salida <= cero;
    else
    tmp <= entrada or paso;
    salida <= tmp REM modulo ;
    end if;
    end process;
    end comportamiento;

    but my compiler tell me that : REM can not have such operands in this
    context.

    anybody can help me.


    Thanks.
     
    Loppy, May 19, 2006
    #1
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  2. Loppy

    Jeremy Ralph Guest

    Are you trying to write synthesizable code? If so you should be aware
    that /, **, mod, and rem are not synthesizable, except for perhaps
    powers of 2 or static values (i.e. values bound at compile-time).

    For behavioural code, the REM operator from Numeric_Std works on
    UNSIGNED, INTEGER, NATURAL, SIGNED -- not sure about std_logic_vector.
    Perhaps try converting tmp and modulo to UNSIGNED before doing the REM
    operation, assigning the result to an UNSIGNED.


    ---
    PDTi [ http://www.productive-eda.com ]
    SpectaReg -- Spec-down code and doc generation for register maps
     
    Jeremy Ralph, May 19, 2006
    #2
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  3. Loppy

    Loppy Guest

    I have tried:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;
    --use IEEE.STD_LOGIC_ARITH.ALL;
    --use IEEE.STD_LOGIC_UNSIGNED.ALL;



    entity incmodL is
    generic ( constant paso: std_logic_vector(7 downto 0):="00000010";
    constant cero: std_logic_vector(7 downto 0):="00000000"
    );

    port ( entrada : in std_logic_vector(7 downto 0);
    modulo : in std_logic_vector(7 downto 0);
    reset : in std_logic;
    salida : inout std_logic_vector(7 downto 0)
    );
    end incmodL;

    architecture comportamiento of incmodL is
    signal tmp : std_logic_vector(7 downto 0):="00000000";
    signal tmp2 : integer;
    begin

    process(entrada,modulo,reset)

    function fmodulo(valor,modl: integer) return integer is
    variable tmp3: integer;
    begin
    if valor < modl then
    return valor;
    else
    tmp3 := valor;

    tmp3:=tmp3-modl;
    while tmp3 >= modl loop
    tmp3:=tmp3-modl;
    end loop;

    return tmp3;

    end if;
    end function fmodulo;

    begin
    if reset='1' then
    salida <= cero;
    else
    tmp <= entrada or paso;

    tmp2 <=
    fmodulo(to_integer(unsigned(tmp)),to_integer(unsigned(modulo)));

    salida <= std_logic_vector(to_unsigned(tmp2,8));

    end if;
    end process;
    end comportamiento;

    but don´t work.
     
    Loppy, May 20, 2006
    #3
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