a microcomputer design problem

Discussion in 'VHDL' started by denken, May 14, 2008.

  1. denken

    denken Guest

    I designed a microcomputer based on the book "VHDL programming by
    example" by Douglas L. Perry.
    The software I use is Quartus II v5.0.
    The device I use is Flex10K EPF10K20RC240-4.

    The memory and cpu could be synthesized separately, but after I
    combined them in my top level entity as follows

    m1 : mem port map (addr, vma, rw, ready,data);
    u1 : cpu port map(clock, reset, ready, addr, rw, vma, data);

    No logic cell was created.

    Does anyone know what is wrong?

    Thanks
     
    denken, May 14, 2008
    #1
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  2. denken

    Guest

    On May 13, 9:26 pm, denken <> wrote:
    > I designed a microcomputer based on the book "VHDL programming by
    > example" by Douglas L. Perry.
    > The software I use is Quartus II v5.0.
    > The device I use is Flex10K EPF10K20RC240-4.
    >
    > The memory and cpu could be synthesized separately, but after I
    > combined them in my top level entity as follows
    >
    > m1 : mem port map (addr, vma, rw, ready,data);
    > u1 : cpu port map(clock, reset, ready, addr, rw, vma, data);
    >
    > No logic cell was created.
    >
    > Does anyone know what is wrong?
    >
    > Thanks


    If you simply cross-connected your CPU bus to your memory bus, and
    left only *inputs* (clk, reset) free, it is likely that the
    synthesizer optimized all of the logic away. The optimizer typically
    assumes that it can delete anything unobservable. If there are no
    outputs to the chip pins, then *everything* is unobservable.

    To prevent this from happening, try connecting your busses (addr, rw,
    etc) to some IO pins on the 10K20 device and resynthesize.

    - Kenn
     
    , May 14, 2008
    #2
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  3. denken

    denken Guest

    On May 13, 7:55 pm, wrote:
    > On May 13, 9:26 pm, denken <> wrote:
    >
    >
    >
    > > I designed a microcomputer based on the book "VHDL programming by
    > > example" by Douglas L. Perry.
    > > The software I use is Quartus II v5.0.
    > > The device I use is Flex10K EPF10K20RC240-4.

    >
    > > The memory and cpu could be synthesized separately, but after I
    > > combined them in my top level entity as follows

    >
    > > m1 : mem port map (addr, vma, rw, ready,data);
    > > u1 : cpu port map(clock, reset, ready, addr, rw, vma, data);

    >
    > > No logic cell was created.

    >
    > > Does anyone know what is wrong?

    >
    > > Thanks

    >
    > If you simply cross-connected your CPU bus to your memory bus, and
    > left only *inputs* (clk, reset) free, it is likely that the
    > synthesizer optimized all of the logic away. The optimizer typically
    > assumes that it can delete anything unobservable. If there are no
    > outputs to the chip pins, then *everything* is unobservable.
    >
    > To prevent this from happening, try connecting your busses (addr, rw,
    > etc) to some IO pins on the 10K20 device and resynthesize.
    >
    > - Kenn


    Thanks, you are right, what I did was just simply connecting cpu bus
    to the memory bus.
    Now the problem is whenever I tried to connect any internal bus to the
    chip pin, it doesn't fit into the device, the error is like this :

    Error: Node "mem:m1|lpm_ram_dq:Memory|altram:sram|q[9]" has non-
    registered write enable-- attempting to initialize a RAM with non-
    registered write enable

    The memory I used is asynchronous, because I don't want to use more
    clock cycles to read and write data from the memory. Thus in the
    lpm_ram_dq generic declaration, LPM_INDATA , LPM_ADDRESS_CONTROL,
    LPM_OUTDATA are unregistered. Is this the reason of the error?
     
    denken, May 14, 2008
    #3
  4. denken wrote:

    > The memory I used is asynchronous,


    Block ram is synchronous.

    > because I don't want to use more
    > clock cycles to read and write data from the memory.


    You could do burst accesses.

    > Thus in the
    > lpm_ram_dq generic declaration, LPM_INDATA , LPM_ADDRESS_CONTROL,
    > LPM_OUTDATA are unregistered. Is this the reason of the error?


    Yes.

    -- Mike Treseler
     
    Mike Treseler, May 14, 2008
    #4
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