a small vhdl problem

Discussion in 'VHDL' started by s_hlu, Sep 24, 2008.

  1. s_hlu

    s_hlu

    Joined:
    Sep 24, 2008
    Messages:
    1
    Location:
    Germany
    Hallo,
    I am new to vhdl, now met a problem and dont know how to solve..:stupido:
    I am implementing somelike Bitwise Arbitration in can bus, now on my bus interface i have 2 ports, txd_o and rxd_i.(one for transmit, one for receive).
    Now i wanna do something like : if(txd_o /= rxd_i) , then sth bla bla.. ----------Now so the problem is obviously that, synthesis says, Object txd_o of mode OUT cannot be read :-(
    So does anyone know, how to solve this ? Or has some more better ideas to implement this ? (Bitwise Arbitration need to compare the value this node sent and the value this node read )
    Thanks a lot !

    Regards,
     
    s_hlu, Sep 24, 2008
    #1
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  2. s_hlu

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
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    Location:
    Denmark
    Try to change OUT with INOUT - this will normally solve the problem
     
    jeppe, Sep 24, 2008
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