Hi, my question is very simple but i cant find any answer to it juste
loocking at xilinx site or reading there data sheets.
My question is :
Do any one have an exemple of template for instantiating xilinx Virtex
II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18
Read the section in the "Virtex II Platform FPGA User Guide" on "Using
Block SelectRAM Memory". This can be downloaded from the Xilinx web
site.
If you want to do simulations use Coregen to create a component with
all the simulation parameters needed, such as all the various delays.
You can still use this for synthesis as well.
If you don't need to do simulations you can just look at the library
guide on block selectRAM and find the one you want, then create your
own component declaration using exactly the same component name as in
the library and the exact same port names as appear on the block
diagrams, and then instantiate this component. This should synthesize
and place and route just like any other Xilinx library primitive, such
as IBUF, OBUF, BUFG, etc.
One thing to remember if you do this, is that depending on the model,
some signals such as DI[x:0], DIP[x:0], DO[x:0] and DOP[x:0] are
always considered to be busses, even if they are only one bit wide. If
the port is only one bit wide for your particular model, then you must
still declare it as a buss, i.e. as std_logic_vector(0 downto 0). If
you just use std_logic, you will get synthesis errors.