A very simple question : RAMB

Discussion in 'VHDL' started by Oleg, Jul 7, 2004.

  1. Oleg

    Oleg Guest

    Hi, my question is very simple but i cant find any answer to it juste
    loocking at xilinx site or reading there data sheets.
    My question is :
    Do any one have an exemple of template for instantiating xilinx Virtex
    II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18
    Oleg, Jul 7, 2004
    #1
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  2. Oleg wrote:
    > Hi, my question is very simple but i cant find any answer to it juste
    > loocking at xilinx site or reading there data sheets.
    > My question is :
    > Do any one have an exemple of template for instantiating xilinx Virtex
    > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18


    Look in the Xilinx directory:

    vhdl/unisim/unisim_VCOM.vhd

    not 100% sure of the filename and path but it is the unisim library you
    want.
    --
    Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
    Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
    Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
    Tim Hubberstey, Jul 7, 2004
    #2
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  3. Oleg

    Sean Durkin Guest

    Oleg wrote:
    > Hi, my question is very simple but i cant find any answer to it juste
    > loocking at xilinx site or reading there data sheets.
    > My question is :
    > Do any one have an exemple of template for instantiating xilinx Virtex
    > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

    Look here:

    http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0027_11.html

    There's example instantiations for all Virtex design elements.

    cu,
    Sean
    Sean Durkin, Jul 7, 2004
    #3
  4. Oleg

    Oleg Guest

    Sean Durkin <> wrote in message news:<>...
    > Oleg wrote:
    > > Hi, my question is very simple but i cant find any answer to it juste
    > > loocking at xilinx site or reading there data sheets.
    > > My question is :
    > > Do any one have an exemple of template for instantiating xilinx Virtex
    > > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

    > Look here:
    >
    > http://toolbox.xilinx.com/docsan/xilinx5/data/docs/lib/lib0027_11.html
    >
    > There's example instantiations for all Virtex design elements.
    >
    > cu,
    > Sean


    Hi,

    Thanks very much guys, the toolbox.xilinx is realy helpfull.
    Oleg, Jul 7, 2004
    #4
  5. (Oleg) wrote in message news:<>...
    > Hi, my question is very simple but i cant find any answer to it juste
    > loocking at xilinx site or reading there data sheets.
    > My question is :
    > Do any one have an exemple of template for instantiating xilinx Virtex
    > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18


    Read the section in the "Virtex II Platform FPGA User Guide" on "Using
    Block SelectRAM Memory". This can be downloaded from the Xilinx web
    site.

    If you want to do simulations use Coregen to create a component with
    all the simulation parameters needed, such as all the various delays.
    You can still use this for synthesis as well.

    If you don't need to do simulations you can just look at the library
    guide on block selectRAM and find the one you want, then create your
    own component declaration using exactly the same component name as in
    the library and the exact same port names as appear on the block
    diagrams, and then instantiate this component. This should synthesize
    and place and route just like any other Xilinx library primitive, such
    as IBUF, OBUF, BUFG, etc.

    One thing to remember if you do this, is that depending on the model,
    some signals such as DI[x:0], DIP[x:0], DO[x:0] and DOP[x:0] are
    always considered to be busses, even if they are only one bit wide. If
    the port is only one bit wide for your particular model, then you must
    still declare it as a buss, i.e. as std_logic_vector(0 downto 0). If
    you just use std_logic, you will get synthesis errors.
    Ralfe Cookson, Jul 7, 2004
    #5
  6. Oleg

    INS122595 Guest

    At the ISE

    Edit => Language Templates => VHDL => Component Instantiation => Block RAM

    If you dont have the ISE download the WebPack from Xilinx site.

    Walter.

    "Oleg" <> a écrit dans le message de
    news:...
    > Hi, my question is very simple but i cant find any answer to it juste
    > loocking at xilinx site or reading there data sheets.
    > My question is :
    > Do any one have an exemple of template for instantiating xilinx Virtex
    > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18
    INS122595, Jul 8, 2004
    #6
  7. Oleg

    Oleg Guest

    (Ralfe Cookson) wrote in message news:<>...
    > (Oleg) wrote in message news:<>...
    > > Hi, my question is very simple but i cant find any answer to it juste
    > > loocking at xilinx site or reading there data sheets.
    > > My question is :
    > > Do any one have an exemple of template for instantiating xilinx Virtex
    > > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18

    >
    > Read the section in the "Virtex II Platform FPGA User Guide" on "Using
    > Block SelectRAM Memory". This can be downloaded from the Xilinx web
    > site.
    >
    > If you want to do simulations use Coregen to create a component with
    > all the simulation parameters needed, such as all the various delays.
    > You can still use this for synthesis as well.
    >
    > If you don't need to do simulations you can just look at the library
    > guide on block selectRAM and find the one you want, then create your
    > own component declaration using exactly the same component name as in
    > the library and the exact same port names as appear on the block
    > diagrams, and then instantiate this component. This should synthesize
    > and place and route just like any other Xilinx library primitive, such
    > as IBUF, OBUF, BUFG, etc.
    >
    > One thing to remember if you do this, is that depending on the model,
    > some signals such as DI[x:0], DIP[x:0], DO[x:0] and DOP[x:0] are
    > always considered to be busses, even if they are only one bit wide. If
    > the port is only one bit wide for your particular model, then you must
    > still declare it as a buss, i.e. as std_logic_vector(0 downto 0). If
    > you just use std_logic, you will get synthesis errors.



    Thnks Ralfe,

    I appreciate your answer too and i have a question for you :
    suppose i am using RAMB16_S2, its address port is of 13 bits, if I use
    only 5 bits of them then Xilinx suggest to connect unused pins to
    logic '1'. Now if the input address bus of my VHDL entity is generic
    (not fixed to 5 bits) how can i handle this ?? do u have any VHDL
    example???

    More over, I am designing a VHDL memory entity data word width (8,16
    or 32 bits witdh) of wich is generic so i am using RAMB16_S9,
    RAMB16_S18 and RAMB16_S36, we know that there adress and data ports
    are of differents width. Each time i want to use one of these 3 RAMB i
    do :

    if data_word = X generate

    RAMB16_SX.......
    .........
    end generate.

    My question still the same : how to handle the generic in a sush
    situation??

    Any help from any one is highly appreciated.
    Oleg, Jul 8, 2004
    #7
  8. Hi Oleg,

    You can perhaps define them via a concatenation

    Take an example:

    Your memory address bus is size 5, your ram port is size 13.

    Take following pseudo code:

    use work.ram_definition_pkg.all; -- The package content the constant
    definition RAM_ADDR_SIZE=13
    ....
    entity myRAM is
    generic (ADDR_SIZE : integer = 5;
    ...);
    ....
    constant tie_high_ram : std_logic_vector ( RAM_ADDR_SIZE -1 downto 0) :=
    (other => '1');
    signal addr_bus_int : std_logic_vector ( RAM_ADDR_SIZE -1 downto 0);
    ....

    addr_bus_int <= tie_high_ram (RAM_ADDR_SIZE -1 downto RAM_ADDR_SIZE -
    ADDR_SIZE) && addr_bus (ADDR_SIZE -1 downto 0);
    ....

    inst_RAMB16_S2 : RAMB16_S2
    port map ( addr => addr_bus_int,
    ....

    Unfortunately this code require that ADDR_SIZE < RAM_ADDR_SIZE.
    A generate can be solve this issue for ADDR_SIZE=RAM_ADDR_SIZE, but I
    don't know any solution in case of ADDR_SIZE > RAM_ADDR_SIZE.

    Bye,
    JaI

    Oleg wrote:

    > (Ralfe Cookson) wrote in message news:<>...
    >
    >
    >> (Oleg) wrote in message news:<>...
    >>
    >>
    >>>Hi, my question is very simple but i cant find any answer to it juste
    >>>loocking at xilinx site or reading there data sheets.
    >>>My question is :
    >>>Do any one have an exemple of template for instantiating xilinx Virtex
    >>>II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18
    >>>
    >>>

    >>Read the section in the "Virtex II Platform FPGA User Guide" on "Using
    >>Block SelectRAM Memory". This can be downloaded from the Xilinx web
    >>site.
    >>
    >>If you want to do simulations use Coregen to create a component with
    >>all the simulation parameters needed, such as all the various delays.
    >>You can still use this for synthesis as well.
    >>
    >>If you don't need to do simulations you can just look at the library
    >>guide on block selectRAM and find the one you want, then create your
    >>own component declaration using exactly the same component name as in
    >>the library and the exact same port names as appear on the block
    >>diagrams, and then instantiate this component. This should synthesize
    >>and place and route just like any other Xilinx library primitive, such
    >>as IBUF, OBUF, BUFG, etc.
    >>
    >>One thing to remember if you do this, is that depending on the model,
    >>some signals such as DI[x:0], DIP[x:0], DO[x:0] and DOP[x:0] are
    >>always considered to be busses, even if they are only one bit wide. If
    >>the port is only one bit wide for your particular model, then you must
    >>still declare it as a buss, i.e. as std_logic_vector(0 downto 0). If
    >>you just use std_logic, you will get synthesis errors.
    >>
    >>

    >
    >
    >Thnks Ralfe,
    >
    >I appreciate your answer too and i have a question for you :
    >suppose i am using RAMB16_S2, its address port is of 13 bits, if I use
    >only 5 bits of them then Xilinx suggest to connect unused pins to
    >logic '1'. Now if the input address bus of my VHDL entity is generic
    >(not fixed to 5 bits) how can i handle this ?? do u have any VHDL
    >example???
    >
    >More over, I am designing a VHDL memory entity data word width (8,16
    >or 32 bits witdh) of wich is generic so i am using RAMB16_S9,
    >RAMB16_S18 and RAMB16_S36, we know that there adress and data ports
    >are of differents width. Each time i want to use one of these 3 RAMB i
    >do :
    >
    >if data_word = X generate
    >
    > RAMB16_SX.......
    > .........
    >end generate.
    >
    >My question still the same : how to handle the generic in a sush
    >situation??
    >
    >Any help from any one is highly appreciated.
    >
    >
    Just an Illusion, Jul 9, 2004
    #8
  9. Oleg

    Oleg Guest

    "INS122595" <> wrote in message news:<>...
    > At the ISE
    >
    > Edit => Language Templates => VHDL => Component Instantiation => Block RAM
    >
    > If you dont have the ISE download the WebPack from Xilinx site.
    >
    > Walter.
    >
    > "Oleg" <> a écrit dans le message de
    > news:...
    > > Hi, my question is very simple but i cant find any answer to it juste
    > > loocking at xilinx site or reading there data sheets.
    > > My question is :
    > > Do any one have an exemple of template for instantiating xilinx Virtex
    > > II single ported RAMB16_S2,RAMB16_9 and RAMB16_S18


    Hi Ralfe,

    I had the same idea like the one yous suggested but i wasnt sure and
    when you are note sure you better ask a fellows ;-).... you know, you
    never realy use as much address as its available in the RAMB
    especially in my case, i never exeed 8 bits adr_bus width. IF
    (condition) generate is very usfull to change to RAMB16_Sx to better
    suit the data size especialy if the words are standard
    (8,16,32,64...bits width).

    Thanks a lot Ralfe for your time, i realy appreciated ;-)
    Oleg, Jul 9, 2004
    #9
  10. Oleg

    Oleg Guest

    Hi Walter, Thank a lot for the truc, its realy funy : the answer is
    right under the nose but we never look there ;-)

    Thanks a lot Walter.


    > > At the ISE
    > >
    > > Edit => Language Templates => VHDL => Component Instantiation => Block RAM
    > >
    > > If you dont have the ISE download the WebPack from Xilinx site.
    > >
    > > Walter.
    Oleg, Jul 14, 2004
    #10
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