A VHDL port map question.

Discussion in 'VHDL' started by BCW0928, Nov 4, 2006.

  1. BCW0928

    BCW0928

    Joined:
    Nov 4, 2006
    Messages:
    1
    Here is the problem.
    I'm design a 32 bits ALU using structure. and our professor want us to break the 32 bits ALU into 8 of 4 bit ALU pieceses. and every 4 bit ALU structure only take 4 bit vector's input with both A and B.
    so at end, The input is 32 bits for both input A and B.
    so my port map will be like following

    four_bit_ALU port map(A=>A(3:0), B=>B(3:0).........)

    where A is 4 bits vector input for the 4 bit ALU structor,
    A(3:0) is where I tried to get the first 4 bits of my 32 bit inputs
    however, it doesn't work out. Does anyone know how to do that?

    or does anyone know how to take the 32 bits input and break it down to eight 4 bits signals, which it will map to my 4 bit ALU.
     
    BCW0928, Nov 4, 2006
    #1
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