About Altera patent application "Logic Cell Supporting Addition ofThree Binary Words"

Discussion in 'VHDL' started by Weng Tianxiang, Jun 14, 2009.

  1. Hi,
    I recently read Altera Stratix II, III and IV device handbook and
    found its 3-bit addition circuit is really a genius invention. But I
    was surprised to find that Altera patent application "Logic Cell
    Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    not been approved to be a patent so far today, even though many Altera
    later patent applications based on the invention have been approved
    for U.S. patents.

    Is anyone knowledgable about the patent application willing to
    transfer the patent application context to me and disclose why it
    hasn't been approved as a U.S. patent.

    My guess is it may never be approved by U.S. Patent Office to be a
    patent, the reason is not its novelty violation, but its context
    didn't disclose enough information about the 3-bit addition circuit, a
    requirement for any patent application to be approved to be a U.S.
    patent. At least those skilled in the art cannot get the idea what is
    done within its circuit having an encircled '+' with 3 inputs and 2
    outputs.

    Altera another sister patent application "Arithmetic Structure is for
    Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.

    Thank you.

    Weng
    Weng Tianxiang, Jun 14, 2009
    #1
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  2. Weng Tianxiang

    rickman Guest

    Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 14, 1:21 pm, Weng Tianxiang <> wrote:
    > Hi,
    > I recently read Altera Stratix II, III and IV device handbook and
    > found its 3-bit addition circuit is really a genius invention. But I
    > was surprised to find that Altera patent application "Logic Cell
    > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    > not been approved to be a patent so far today, even though many Altera
    > later patent applications based on the invention have been approved
    > for U.S. patents.
    >
    > Is anyone knowledgable about the patent application willing to
    > transfer the patent application context to me and disclose why it
    > hasn't been approved as a U.S. patent.
    >
    > My guess is it may never be approved by U.S. Patent Office to be a
    > patent, the reason is not its novelty violation, but its context
    > didn't disclose enough information about the 3-bit addition circuit, a
    > requirement for any patent application to be approved to be a U.S.
    > patent. At least those skilled in the art cannot get the idea what is
    > done within its circuit having an encircled '+' with 3 inputs and 2
    > outputs.
    >
    > Altera another sister patent application "Arithmetic Structure is for
    > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.
    >
    > Thank you.
    >
    > Weng


    I don't know why Altera wouldn't disclose info on the structure being
    used in a device. It is relatively inexpensive to reverse engineer a
    chip, so if it is not disclosed in a patent, it is not protected and
    is vulnerable to being copied.

    What exactly *does* the patent claim? Maybe the design inside the
    circled + is not really novel and only the design around the circle is
    novel enough to be patented?

    In general, I think a three in put adder is *very useful*. I've never
    seen such a circuit, I guess the carry chain has multiple bits, eh?

    Rick
    rickman, Jun 15, 2009
    #2
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  3. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 4:36 am, rickman <> wrote:
    > On Jun 14, 1:21 pm, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > Hi,
    > > I recently read Altera Stratix II, III and IV device handbook and
    > > found its 3-bit addition circuit is really a genius invention. But I
    > > was surprised to find that Altera patent application "Logic Cell
    > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    > > not been approved to be a patent so far today, even though many Altera
    > > later patent applications based on the invention have been approved
    > > for U.S. patents.

    >
    > > Is anyone knowledgable about the patent application willing to
    > > transfer the patent application context to me and disclose why it
    > > hasn't been approved as a U.S. patent.

    >
    > > My guess is it may never be approved by U.S. Patent Office to be a
    > > patent, the reason is not its novelty violation, but its context
    > > didn't disclose enough information about the 3-bit addition circuit, a
    > > requirement for any patent application to be approved to be a U.S.
    > > patent. At least those skilled in the art cannot get the idea what is
    > > done within its circuit having an encircled '+' with 3 inputs and 2
    > > outputs.

    >
    > > Altera another sister patent application "Arithmetic Structure is for
    > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.

    >
    > > Thank you.

    >
    > > Weng

    >
    > I don't know why Altera wouldn't disclose info on the structure being
    > used in a device.  It is relatively inexpensive to reverse engineer a
    > chip, so if it is not disclosed in a patent, it is not protected and
    > is vulnerable to being copied.
    >
    > What exactly *does* the patent claim?  Maybe the design inside the
    > circled + is not really novel and only the design around the circle is
    > novel enough to be patented?
    >
    > In general, I think a three in put adder is *very useful*.  I've never
    > seen such a circuit, I guess the carry chain has multiple bits, eh?
    >
    > Rick- Hide quoted text -
    >
    > - Show quoted text -



    Hi Rick,
    Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
    shows the invention circuit:
    http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf

    Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
    describes two applications: multiplication and correlation function.

    Any other applications? With multiplier hardware structure specially
    introduced in FPGA, is multiplication circuit still used for
    multiplication?

    Weng
    Weng Tianxiang, Jun 15, 2009
    #3
  4. Weng Tianxiang

    rickman Guest

    Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 10:13 am, Weng Tianxiang <> wrote:
    > On Jun 15, 4:36 am, rickman <> wrote:
    >
    >
    >
    > > On Jun 14, 1:21 pm, Weng Tianxiang <> wrote:

    >
    > > > Hi,
    > > > I recently read Altera Stratix II, III and IV device handbook and
    > > > found its 3-bit addition circuit is really a genius invention. But I
    > > > was surprised to find that Altera patent application "Logic Cell
    > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    > > > not been approved to be a patent so far today, even though many Altera
    > > > later patent applications based on the invention have been approved
    > > > for U.S. patents.

    >
    > > > Is anyone knowledgable about the patent application willing to
    > > > transfer the patent application context to me and disclose why it
    > > > hasn't been approved as a U.S. patent.

    >
    > > > My guess is it may never be approved by U.S. Patent Office to be a
    > > > patent, the reason is not its novelty violation, but its context
    > > > didn't disclose enough information about the 3-bit addition circuit, a
    > > > requirement for any patent application to be approved to be a U.S.
    > > > patent. At least those skilled in the art cannot get the idea what is
    > > > done within its circuit having an encircled '+' with 3 inputs and 2
    > > > outputs.

    >
    > > > Altera another sister patent application "Arithmetic Structure is for
    > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.

    >
    > > > Thank you.

    >
    > > > Weng

    >
    > > I don't know why Altera wouldn't disclose info on the structure being
    > > used in a device. It is relatively inexpensive to reverse engineer a
    > > chip, so if it is not disclosed in a patent, it is not protected and
    > > is vulnerable to being copied.

    >
    > > What exactly *does* the patent claim? Maybe the design inside the
    > > circled + is not really novel and only the design around the circle is
    > > novel enough to be patented?

    >
    > > In general, I think a three in put adder is *very useful*. I've never
    > > seen such a circuit, I guess the carry chain has multiple bits, eh?

    >
    > > Rick- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > Hi Rick,
    > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
    > shows the invention circuit:http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf
    >
    > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
    > describes two applications: multiplication and correlation function.
    >
    > Any other applications? With multiplier hardware structure specially
    > introduced in FPGA, is multiplication circuit still used for
    > multiplication?


    Although they show the interconnections being used, they don't show
    the logic implemented in the LUTs. The carry from one bit to the next
    is done with two signals each of which has the same weight. As far as
    I can tell, this is just a pair of cascaded adders, the first done in
    the LUTs and the second done in dedicated hardware. The only novelty
    is that instead of adding two inputs with one adder chain (the LUTs)
    and then adding the result to the third input with the dedicated
    hardware chain, they add all three input bits using the LUTs and feed
    both carry bits into the dedicated hardware chain which means the
    carry chain always uses the fast, dedicated hardware.

    Does that sound like a patent worthy invention to you? I don't really
    know what is and what is not worthy of a patent. But other patents
    "based" on this patent will not be affected by the validity of this
    patent. Even if this patent is upheld, ***I*** could patent some
    additional feature that uses this design as a starting point. I just
    can't build it without permission from the patent holder of the
    original design. Still, this means he/she couldn't use my idea
    without my permission either.

    Rick
    rickman, Jun 15, 2009
    #4
  5. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 8:39 am, rickman <> wrote:
    > On Jun 15, 10:13 am, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > On Jun 15, 4:36 am, rickman <> wrote:

    >
    > > > On Jun 14, 1:21 pm, Weng Tianxiang <> wrote:

    >
    > > > > Hi,
    > > > > I recently read Altera Stratix II, III and IV device handbook and
    > > > > found its 3-bit addition circuit is really a genius invention. But I
    > > > > was surprised to find that Altera patent application "Logic Cell
    > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    > > > > not been approved to be a patent so far today, even though many Altera
    > > > > later patent applications based on the invention have been approved
    > > > > for U.S. patents.

    >
    > > > > Is anyone knowledgable about the patent application willing to
    > > > > transfer the patent application context to me and disclose why it
    > > > > hasn't been approved as a U.S. patent.

    >
    > > > > My guess is it may never be approved by U.S. Patent Office to be a
    > > > > patent, the reason is not its novelty violation, but its context
    > > > > didn't disclose enough information about the 3-bit addition circuit, a
    > > > > requirement for any patent application to be approved to be a U.S.
    > > > > patent. At least those skilled in the art cannot get the idea what is
    > > > > done within its circuit having an encircled '+' with 3 inputs and 2
    > > > > outputs.

    >
    > > > > Altera another sister patent application "Arithmetic Structure is for
    > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate..

    >
    > > > > Thank you.

    >
    > > > > Weng

    >
    > > > I don't know why Altera wouldn't disclose info on the structure being
    > > > used in a device.  It is relatively inexpensive to reverse engineer a
    > > > chip, so if it is not disclosed in a patent, it is not protected and
    > > > is vulnerable to being copied.

    >
    > > > What exactly *does* the patent claim?  Maybe the design inside the
    > > > circled + is not really novel and only the design around the circle is
    > > > novel enough to be patented?

    >
    > > > In general, I think a three in put adder is *very useful*.  I've never
    > > > seen such a circuit, I guess the carry chain has multiple bits, eh?

    >
    > > > Rick- Hide quoted text -

    >
    > > > - Show quoted text -

    >
    > > Hi Rick,
    > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
    > > shows the invention circuit:http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf

    >
    > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
    > > describes two applications: multiplication and correlation function.

    >
    > > Any other applications? With multiplier hardware structure specially
    > > introduced in FPGA, is multiplication circuit still used for
    > > multiplication?

    >
    > Although they show the interconnections being used, they don't show
    > the logic implemented in the LUTs.  The carry from one bit to the next
    > is done with two signals each of which has the same weight.  As far as
    > I can tell, this is just a pair of cascaded adders, the first done in
    > the LUTs and the second done in dedicated hardware.  The only novelty
    > is that instead of adding two inputs with one adder chain (the LUTs)
    > and then adding the result to the third input with the dedicated
    > hardware chain, they add all three input bits using the LUTs and feed
    > both carry bits into the dedicated hardware chain which means the
    > carry chain always uses the fast, dedicated hardware.
    >
    > Does that sound like a patent worthy invention to you?  I don't really
    > know what is and what is not worthy of a patent.  But other patents
    > "based" on this patent will not be affected by the validity of this
    > patent.  Even if this patent is upheld, ***I*** could patent some
    > additional feature that uses this design as a starting point.  I just
    > can't build it without permission from the patent holder of the
    > original design.  Still, this means he/she couldn't use my idea
    > without my permission either.
    >
    > Rick- Hide quoted text -
    >
    > - Show quoted text -


    Hi Rick,
    There are two novel points there:
    1. It transfers 3 adders into 2 adders which was described very clear:
    nobody before had invented that point.
    2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose
    internal structure wasn't shown.
    3. I am sure there may be more than 20 claims in the application as
    Altera patent claim trandition goes.

    Weng
    Weng Tianxiang, Jun 15, 2009
    #5
  6. Weng Tianxiang

    OutputLogic Guest

    Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    You can try to go to USPTO database and lookup the history of this
    patent application.
    It's not under the patent search, but under "http://www.uspto.gov" ->
    "Patents" -> "view in PAIR" -> "public PAIR".
    This database contains a complete history of the patent, including the
    correspondence with patent examiners, etc.
    Also, can you post the patent application number.

    - outputlogic

    http://outputlogic.com
    OutputLogic, Jun 15, 2009
    #6
  7. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 9:23 am, OutputLogic <> wrote:
    > You can try to go to USPTO database and lookup the history of this
    > patent application.
    > It's not under the patent search, but under "http://www.uspto.gov" ->
    > "Patents" -> "view in PAIR" -> "public PAIR".
    > This database contains a complete history of the patent, including the
    > correspondence with patent examiners, etc.
    > Also, can you post the patent application number.
    >
    > - outputlogic
    >
    > http://outputlogic.com


    Hi,
    Its application number is 10/718,968 filed on November 21, 2003.

    Weng
    Weng Tianxiang, Jun 15, 2009
    #7
  8. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 9:23 am, OutputLogic <> wrote:
    > You can try to go to USPTO database and lookup the history of this
    > patent application.
    > It's not under the patent search, but under "http://www.uspto.gov" ->
    > "Patents" -> "view in PAIR" -> "public PAIR".
    > This database contains a complete history of the patent, including the
    > correspondence with patent examiners, etc.
    > Also, can you post the patent application number.
    >
    > - outputlogic
    >
    > http://outputlogic.com


    Hi OutputLogic,
    Thank you for your information.

    I had searched the website before I posed this message and got the
    error information:
    "Sorry, the entered Application Number "10/718968" is not available.
    The number may have been incorrectly typed, or assigned to an
    application
    that is not yet available for public inspection."

    I don't know why I got the error message.

    10/718968 is available from reference literature in the invention:
    "Programmable Logic Device Having Complex Logic Blocks with Improved
    Logic Cell Functionality", patent number 7,394,287, by Alera from
    following website:
    http://www.google.com/patents/about...inm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is=

    Weng
    Weng Tianxiang, Jun 15, 2009
    #8
  9. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 8:39 am, rickman <> wrote:
    > On Jun 15, 10:13 am, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > On Jun 15, 4:36 am, rickman <> wrote:

    >
    > > > On Jun 14, 1:21 pm, Weng Tianxiang <> wrote:

    >
    > > > > Hi,
    > > > > I recently read Altera Stratix II, III and IV device handbook and
    > > > > found its 3-bit addition circuit is really a genius invention. But I
    > > > > was surprised to find that Altera patent application "Logic Cell
    > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    > > > > not been approved to be a patent so far today, even though many Altera
    > > > > later patent applications based on the invention have been approved
    > > > > for U.S. patents.

    >
    > > > > Is anyone knowledgable about the patent application willing to
    > > > > transfer the patent application context to me and disclose why it
    > > > > hasn't been approved as a U.S. patent.

    >
    > > > > My guess is it may never be approved by U.S. Patent Office to be a
    > > > > patent, the reason is not its novelty violation, but its context
    > > > > didn't disclose enough information about the 3-bit addition circuit, a
    > > > > requirement for any patent application to be approved to be a U.S.
    > > > > patent. At least those skilled in the art cannot get the idea what is
    > > > > done within its circuit having an encircled '+' with 3 inputs and 2
    > > > > outputs.

    >
    > > > > Altera another sister patent application "Arithmetic Structure is for
    > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate..

    >
    > > > > Thank you.

    >
    > > > > Weng

    >
    > > > I don't know why Altera wouldn't disclose info on the structure being
    > > > used in a device.  It is relatively inexpensive to reverse engineer a
    > > > chip, so if it is not disclosed in a patent, it is not protected and
    > > > is vulnerable to being copied.

    >
    > > > What exactly *does* the patent claim?  Maybe the design inside the
    > > > circled + is not really novel and only the design around the circle is
    > > > novel enough to be patented?

    >
    > > > In general, I think a three in put adder is *very useful*.  I've never
    > > > seen such a circuit, I guess the carry chain has multiple bits, eh?

    >
    > > > Rick- Hide quoted text -

    >
    > > > - Show quoted text -

    >
    > > Hi Rick,
    > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
    > > shows the invention circuit:http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf

    >
    > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
    > > describes two applications: multiplication and correlation function.

    >
    > > Any other applications? With multiplier hardware structure specially
    > > introduced in FPGA, is multiplication circuit still used for
    > > multiplication?

    >
    > Although they show the interconnections being used, they don't show
    > the logic implemented in the LUTs.  The carry from one bit to the next
    > is done with two signals each of which has the same weight.  As far as
    > I can tell, this is just a pair of cascaded adders, the first done in
    > the LUTs and the second done in dedicated hardware.  The only novelty
    > is that instead of adding two inputs with one adder chain (the LUTs)
    > and then adding the result to the third input with the dedicated
    > hardware chain, they add all three input bits using the LUTs and feed
    > both carry bits into the dedicated hardware chain which means the
    > carry chain always uses the fast, dedicated hardware.
    >
    > Does that sound like a patent worthy invention to you?  I don't really
    > know what is and what is not worthy of a patent.  But other patents
    > "based" on this patent will not be affected by the validity of this
    > patent.  Even if this patent is upheld, ***I*** could patent some
    > additional feature that uses this design as a starting point.  I just
    > can't build it without permission from the patent holder of the
    > original design.  Still, this means he/she couldn't use my idea
    > without my permission either.
    >
    > Rick- Hide quoted text -
    >
    > - Show quoted text -


    Hi Rick,
    "The only novelty
    is that instead of adding two inputs with one adder chain (the LUTs)
    and then adding the result to the third input with the dedicated
    hardware chain, they add all three input bits using the LUTs and feed
    both carry bits into the dedicated hardware chain which means the
    carry chain always uses the fast, dedicated hardware. "

    The method I found was invented as early as 1963 by C.S. Wallace in
    paper "A suggestion for a Fast Multiplier"
    http://www.caip.rutgers.edu/~bushnell/dsmdesign/wallacepaper.pdf

    The circuit circled in '+' with 3 inputs and 2 outputs is novelty in
    my opinion, but they didn't disclose it.

    Weng
    Weng Tianxiang, Jun 16, 2009
    #9
  10. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 5:06 pm, Muzaffer Kal <> wrote:
    > On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang
    >
    > <> wrote:
    > >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in
    > >my opinion, but they didn't disclose it.

    >
    > It would be interesting to see if it's anything other than a 3:2
    > compressor.
    > --
    > Muzaffer Kal
    >
    > DSPIA INC.
    > ASIC/FPGA Design Services
    >
    > http://www.dspia.com


    Here is another good reference published in 1994 by Stanford Ph. D
    student Gary W. Bewick as his dissatation paper.

    ftp://reports.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf,
    page 34 where a 3:2 compressor was shown graphically.

    Weng
    Weng Tianxiang, Jun 16, 2009
    #10
  11. Weng Tianxiang

    rickman Guest

    Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 12:22 pm, Weng Tianxiang <> wrote:
    > On Jun 15, 8:39 am, rickman <> wrote:
    >
    >
    >
    > > On Jun 15, 10:13 am, Weng Tianxiang <> wrote:

    >
    > > > On Jun 15, 4:36 am, rickman <> wrote:

    >
    > > > > On Jun 14, 1:21 pm, Weng Tianxiang <> wrote:

    >
    > > > > > Hi,
    > > > > > I recently read Altera Stratix II, III and IV device handbook and
    > > > > > found its 3-bit addition circuit is really a genius invention. But I
    > > > > > was surprised to find that Altera patent application "Logic Cell
    > > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    > > > > > not been approved to be a patent so far today, even though many Altera
    > > > > > later patent applications based on the invention have been approved
    > > > > > for U.S. patents.

    >
    > > > > > Is anyone knowledgable about the patent application willing to
    > > > > > transfer the patent application context to me and disclose why it
    > > > > > hasn't been approved as a U.S. patent.

    >
    > > > > > My guess is it may never be approved by U.S. Patent Office to be a
    > > > > > patent, the reason is not its novelty violation, but its context
    > > > > > didn't disclose enough information about the 3-bit addition circuit, a
    > > > > > requirement for any patent application to be approved to be a U.S..
    > > > > > patent. At least those skilled in the art cannot get the idea what is
    > > > > > done within its circuit having an encircled '+' with 3 inputs and 2
    > > > > > outputs.

    >
    > > > > > Altera another sister patent application "Arithmetic Structure is for
    > > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.

    >
    > > > > > Thank you.

    >
    > > > > > Weng

    >
    > > > > I don't know why Altera wouldn't disclose info on the structure being
    > > > > used in a device.  It is relatively inexpensive to reverse engineer a
    > > > > chip, so if it is not disclosed in a patent, it is not protected and
    > > > > is vulnerable to being copied.

    >
    > > > > What exactly *does* the patent claim?  Maybe the design inside the
    > > > > circled + is not really novel and only the design around the circle is
    > > > > novel enough to be patented?

    >
    > > > > In general, I think a three in put adder is *very useful*.  I've never
    > > > > seen such a circuit, I guess the carry chain has multiple bits, eh?

    >
    > > > > Rick- Hide quoted text -

    >
    > > > > - Show quoted text -

    >
    > > > Hi Rick,
    > > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
    > > > shows the invention circuit:http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf

    >
    > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
    > > > describes two applications: multiplication and correlation function.

    >
    > > > Any other applications? With multiplier hardware structure specially
    > > > introduced in FPGA, is multiplication circuit still used for
    > > > multiplication?

    >
    > > Although they show the interconnections being used, they don't show
    > > the logic implemented in the LUTs.  The carry from one bit to the next
    > > is done with two signals each of which has the same weight.  As far as
    > > I can tell, this is just a pair of cascaded adders, the first done in
    > > the LUTs and the second done in dedicated hardware.  The only novelty
    > > is that instead of adding two inputs with one adder chain (the LUTs)
    > > and then adding the result to the third input with the dedicated
    > > hardware chain, they add all three input bits using the LUTs and feed
    > > both carry bits into the dedicated hardware chain which means the
    > > carry chain always uses the fast, dedicated hardware.

    >
    > > Does that sound like a patent worthy invention to you?  I don't really
    > > know what is and what is not worthy of a patent.  But other patents
    > > "based" on this patent will not be affected by the validity of this
    > > patent.  Even if this patent is upheld, ***I*** could patent some
    > > additional feature that uses this design as a starting point.  I just
    > > can't build it without permission from the patent holder of the
    > > original design.  Still, this means he/she couldn't use my idea
    > > without my permission either.

    >
    > > Rick- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > Hi Rick,
    > There are two novel points there:
    > 1. It transfers 3 adders into 2 adders which was described very clear:
    > nobody before had invented that point.


    No, it is not 3 adders using 2 adders, it is always just 2 adders.
    The only difference is that there is only one cascaded chain. There
    are two carries between each bit of the adder, sort of like a
    "Propagate/Generate" style of carry, only one results in a chained
    delay calculation. But I don't see any real advantage to that. I
    think the real advantage of this circuit is that it takes advantage of
    the large, 6 input LUT by breaking it into dual 4 input LUTs... but
    wait, that is still wasting half the 6 input LUTs. So it is really
    just an optimization of their particular architecture.

    The only possible novelty here is that they are doing this in an
    FPGA.


    > 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose
    > internal structure wasn't shown.


    Yep, that is because that part is not very patentable, in my opinion.
    You don't put anything in a patent that is not patentable. Anything
    you don't explain in a patent is not part of it.


    > 3. I am sure there may be more than 20 claims in the application as
    > Altera patent claim trandition goes.


    Sure, any patent attorney worth his salt is going to put as many
    claims in as possible. If I understand correctly any claim can stand
    alone even if the others are struck down.

    Rick
    rickman, Jun 16, 2009
    #11
  12. Weng Tianxiang

    rickman Guest

    Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 8:06 pm, Muzaffer Kal <> wrote:
    > On Mon, 15 Jun 2009 16:44:19 -0700 (PDT), Weng Tianxiang
    >
    > <> wrote:
    > >The circuit circled in '+' with 3 inputs and 2 outputs is novelty in
    > >my opinion, but they didn't disclose it.

    >
    > It would be interesting to see if it's anything other than a 3:2
    > compressor.



    Someone is missing something. What is the three input, two output
    circuit? Each bit of the adder has five inputs and three outputs.
    The three addend inputs can add up to 3 and with the two carry inputs
    the total can be up to five requiring two carrie outputs of weight 2
    and the sum output of weight 1. Of course, I am looking at the data
    sheet and I guess you are looking at the patent.

    Rick
    rickman, Jun 16, 2009
    #12
  13. Weng Tianxiang

    rickman Guest

    Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 1:39 pm, Weng Tianxiang <> wrote:
    > On Jun 15, 9:23 am, OutputLogic <> wrote:
    >
    > > You can try to go to USPTO database and lookup the history of this
    > > patent application.
    > > It's not under the patent search, but under "http://www.uspto.gov" ->
    > > "Patents" -> "view in PAIR" -> "public PAIR".
    > > This database contains a complete history of the patent, including the
    > > correspondence with patent examiners, etc.
    > > Also, can you post the patent application number.

    >
    > > - outputlogic

    >
    > >http://outputlogic.com

    >
    > Hi OutputLogic,
    > Thank you for your information.
    >
    > I had searched the website before I posed this message and got the
    > error information:
    > "Sorry, the entered Application Number "10/718968" is not available.
    > The number may have been incorrectly typed, or assigned to an
    > application
    > that is not yet available for public inspection."
    >
    > I don't know why I got the error message.
    >
    > 10/718968 is available from reference literature in the invention:
    > "Programmable Logic Device Having Complex Logic Blocks with Improved
    > Logic Cell Functionality", patent number 7,394,287, by Alera from
    > following website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287...
    >
    > Weng


    7,394,287 is the patent number. It works for me at the USPTO. What
    is the number you are searching for?

    Rick
    rickman, Jun 16, 2009
    #13
  14. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 9:25 pm, rickman <> wrote:
    > On Jun 15, 12:22 pm, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > On Jun 15, 8:39 am, rickman <> wrote:

    >
    > > > On Jun 15, 10:13 am, Weng Tianxiang <> wrote:

    >
    > > > > On Jun 15, 4:36 am, rickman <> wrote:

    >
    > > > > > On Jun 14, 1:21 pm, Weng Tianxiang <> wrote:

    >
    > > > > > > Hi,
    > > > > > > I recently read Altera Stratix II, III and IV device handbook and
    > > > > > > found its 3-bit addition circuit is really a genius invention. But I
    > > > > > > was surprised to find that Altera patent application "Logic Cell
    > > > > > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003 has
    > > > > > > not been approved to be a patent so far today, even though many Altera
    > > > > > > later patent applications based on the invention have been approved
    > > > > > > for U.S. patents.

    >
    > > > > > > Is anyone knowledgable about the patent application willing to
    > > > > > > transfer the patent application context to me and disclose why it
    > > > > > > hasn't been approved as a U.S. patent.

    >
    > > > > > > My guess is it may never be approved by U.S. Patent Office to be a
    > > > > > > patent, the reason is not its novelty violation, but its context
    > > > > > > didn't disclose enough information about the 3-bit addition circuit, a
    > > > > > > requirement for any patent application to be approved to be a U..S.
    > > > > > > patent. At least those skilled in the art cannot get the idea what is
    > > > > > > done within its circuit having an encircled '+' with 3 inputs and 2
    > > > > > > outputs.

    >
    > > > > > > Altera another sister patent application "Arithmetic Structure is for
    > > > > > > Programmable Logic Device" filed on Oct. 23, 2003 has the same fate.

    >
    > > > > > > Thank you.

    >
    > > > > > > Weng

    >
    > > > > > I don't know why Altera wouldn't disclose info on the structure being
    > > > > > used in a device.  It is relatively inexpensive to reverse engineer a
    > > > > > chip, so if it is not disclosed in a patent, it is not protected and
    > > > > > is vulnerable to being copied.

    >
    > > > > > What exactly *does* the patent claim?  Maybe the design inside the
    > > > > > circled + is not really novel and only the design around the circle is
    > > > > > novel enough to be patented?

    >
    > > > > > In general, I think a three in put adder is *very useful*.  I've never
    > > > > > seen such a circuit, I guess the carry chain has multiple bits, eh?

    >
    > > > > > Rick- Hide quoted text -

    >
    > > > > > - Show quoted text -

    >
    > > > > Hi Rick,
    > > > > Here is a link to Stratix IV Device Handbook Volumn 1 and page 43
    > > > > shows the invention circuit:http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf

    >
    > > > > Why is it very useful? In the Stratix IV Device Handbook Volumn 1, it
    > > > > describes two applications: multiplication and correlation function..

    >
    > > > > Any other applications? With multiplier hardware structure specially
    > > > > introduced in FPGA, is multiplication circuit still used for
    > > > > multiplication?

    >
    > > > Although they show the interconnections being used, they don't show
    > > > the logic implemented in the LUTs.  The carry from one bit to the next
    > > > is done with two signals each of which has the same weight.  As far as
    > > > I can tell, this is just a pair of cascaded adders, the first done in
    > > > the LUTs and the second done in dedicated hardware.  The only novelty
    > > > is that instead of adding two inputs with one adder chain (the LUTs)
    > > > and then adding the result to the third input with the dedicated
    > > > hardware chain, they add all three input bits using the LUTs and feed
    > > > both carry bits into the dedicated hardware chain which means the
    > > > carry chain always uses the fast, dedicated hardware.

    >
    > > > Does that sound like a patent worthy invention to you?  I don't really
    > > > know what is and what is not worthy of a patent.  But other patents
    > > > "based" on this patent will not be affected by the validity of this
    > > > patent.  Even if this patent is upheld, ***I*** could patent some
    > > > additional feature that uses this design as a starting point.  I just
    > > > can't build it without permission from the patent holder of the
    > > > original design.  Still, this means he/she couldn't use my idea
    > > > without my permission either.

    >
    > > > Rick- Hide quoted text -

    >
    > > > - Show quoted text -

    >
    > > Hi Rick,
    > > There are two novel points there:
    > > 1. It transfers 3 adders into 2 adders which was described very clear:
    > > nobody before had invented that point.

    >
    > No, it is not 3 adders using 2 adders, it is always just 2 adders.
    > The only difference is that there is only one cascaded chain.  There
    > are two carries between each bit of the adder, sort of like a
    > "Propagate/Generate" style of carry, only one results in a chained
    > delay calculation.  But I don't see any real advantage to that.  I
    > think the real advantage of this circuit is that it takes advantage of
    > the large, 6 input LUT by breaking it into dual 4 input LUTs... but
    > wait, that is still wasting half the 6 input LUTs.  So it is really
    > just an optimization of their particular architecture.
    >
    > The only possible novelty here is that they are doing this in an
    > FPGA.
    >
    > > 2. Circuit is marked by circled '+' with 3 inputs and 2 outputs whose
    > > internal structure wasn't shown.

    >
    > Yep, that is because that part is not very patentable, in my opinion.
    > You don't put anything in a patent that is not patentable.  Anything
    > you don't explain in a patent is not part of it.
    >
    > > 3. I am sure there may be more than 20 claims in the application as
    > > Altera patent claim trandition goes.

    >
    > Sure, any patent attorney worth his salt is going to put as many
    > claims in as possible.  If I understand correctly any claim can stand
    > alone even if the others are struck down.
    >
    > Rick- Hide quoted text -
    >
    > - Show quoted text -


    Hi Rick,
    "No, it is not 3 adders using 2 adders, it is always just 2 adders.
    The only difference is that there is only one cascaded chain. There
    are two carries between each bit of the adder, sort of like a
    "Propagate/Generate" style of carry, only one results in a chained
    delay calculation. But I don't see any real advantage to that. I
    think the real advantage of this circuit is that it takes advantage
    of
    the large, 6 input LUT by breaking it into dual 4 input LUTs... but
    wait, that is still wasting half the 6 input LUTs. So it is really
    just an optimization of their particular architecture.

    The only possible novelty here is that they are doing this in an
    FPGA. "

    Thank you for your comments.

    You are right. I realized it after I posed the message and re-read
    other papers about 3:2 compressor and I didn't correct it myself.
    Weng Tianxiang, Jun 16, 2009
    #14
  15. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 15, 9:41 pm, rickman <> wrote:
    > On Jun 15, 1:39 pm, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > On Jun 15, 9:23 am, OutputLogic <> wrote:

    >
    > > > You can try to go to USPTO database and lookup the history of this
    > > > patent application.
    > > > It's not under the patent search, but under "http://www.uspto.gov" ->
    > > > "Patents" -> "view in PAIR" -> "public PAIR".
    > > > This database contains a complete history of the patent, including the
    > > > correspondence with patent examiners, etc.
    > > > Also, can you post the patent application number.

    >
    > > > - outputlogic

    >
    > > >http://outputlogic.com

    >
    > > Hi OutputLogic,
    > > Thank you for your information.

    >
    > > I had searched the website before I posed this message and got the
    > > error information:
    > > "Sorry, the entered Application Number "10/718968" is not available.
    > > The number may have been incorrectly typed, or assigned to an
    > > application
    > > that is not yet available for public inspection."

    >
    > > I don't know why I got the error message.

    >
    > > 10/718968 is available from reference literature in the invention:
    > > "Programmable Logic Device Having Complex Logic Blocks with Improved
    > > Logic Cell Functionality", patent number 7,394,287, by Alera from
    > > following website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287...

    >
    > > Weng

    >
    > 7,394,287 is the patent number.  It works for me at the USPTO.  What
    > is the number you are searching for?
    >
    > Rick- Hide quoted text -
    >
    > - Show quoted text -


    Hi Rick,
    I have tried to find the text and its drawings of patent application
    "Logic Cell
    Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US
    application number 10/718968, but it must pay to get its context from
    USPTO, even though it was in public domain about 6 years ago.

    Can you help get the context and drawings from USPTO for me?

    Weng
    Weng Tianxiang, Jun 16, 2009
    #15
  16. Weng Tianxiang

    rickman Guest

    Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 16, 9:34 am, Weng Tianxiang <> wrote:
    > On Jun 15, 9:41 pm, rickman <> wrote:
    >
    >
    >
    > > On Jun 15, 1:39 pm, Weng Tianxiang <> wrote:

    >
    > > > On Jun 15, 9:23 am, OutputLogic <> wrote:

    >
    > > > > You can try to go to USPTO database and lookup the history of this
    > > > > patent application.
    > > > > It's not under the patent search, but under "http://www.uspto.gov" ->
    > > > > "Patents" -> "view in PAIR" -> "public PAIR".
    > > > > This database contains a complete history of the patent, including the
    > > > > correspondence with patent examiners, etc.
    > > > > Also, can you post the patent application number.

    >
    > > > > - outputlogic

    >
    > > > >http://outputlogic.com

    >
    > > > Hi OutputLogic,
    > > > Thank you for your information.

    >
    > > > I had searched the website before I posed this message and got the
    > > > error information:
    > > > "Sorry, the entered Application Number "10/718968" is not available.
    > > > The number may have been incorrectly typed, or assigned to an
    > > > application
    > > > that is not yet available for public inspection."

    >
    > > > I don't know why I got the error message.

    >
    > > > 10/718968 is available from reference literature in the invention:
    > > > "Programmable Logic Device Having Complex Logic Blocks with Improved
    > > > Logic Cell Functionality", patent number 7,394,287, by Alera from
    > > > following website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287...

    >
    > > > Weng

    >
    > > 7,394,287 is the patent number.  It works for me at the USPTO.  What
    > > is the number you are searching for?

    >
    > > Rick- Hide quoted text -

    >
    > > - Show quoted text -

    >
    > Hi Rick,
    > I have tried to find the text and its drawings of patent application
    > "Logic Cell
    > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US
    > application number 10/718968, but it must pay to get its context from
    > USPTO, even though it was in public domain about 6 years ago.
    >
    > Can you help get the context and drawings from USPTO for me?
    >
    > Weng


    Where did you get the above info? That does not appear to be a valid
    document number. It needs to have 11 digits where the first four
    appear to be the year.
    I searched on "Three Binary Words" in the title and came up with
    nothing.

    I did search on this for patents and found this one which I think is
    interesting... maybe this is why the adder is just a plus sign with a
    circle... 4,783,757. Note that the owner is Intel, not Altera.

    Rick

    Rick
    rickman, Jun 16, 2009
    #16
  17. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 16, 8:51 am, rickman <> wrote:
    > On Jun 16, 9:34 am, Weng Tianxiang <> wrote:
    >
    >
    >
    >
    >
    > > On Jun 15, 9:41 pm, rickman <> wrote:

    >
    > > > On Jun 15, 1:39 pm, Weng Tianxiang <> wrote:

    >
    > > > > On Jun 15, 9:23 am, OutputLogic <> wrote:

    >
    > > > > > You can try to go to USPTO database and lookup the history of this
    > > > > > patent application.
    > > > > > It's not under the patent search, but under "http://www.uspto.gov" ->
    > > > > > "Patents" -> "view in PAIR" -> "public PAIR".
    > > > > > This database contains a complete history of the patent, including the
    > > > > > correspondence with patent examiners, etc.
    > > > > > Also, can you post the patent application number.

    >
    > > > > > - outputlogic

    >
    > > > > >http://outputlogic.com

    >
    > > > > Hi OutputLogic,
    > > > > Thank you for your information.

    >
    > > > > I had searched the website before I posed this message and got the
    > > > > error information:
    > > > > "Sorry, the entered Application Number "10/718968" is not available..
    > > > > The number may have been incorrectly typed, or assigned to an
    > > > > application
    > > > > that is not yet available for public inspection."

    >
    > > > > I don't know why I got the error message.

    >
    > > > > 10/718968 is available from reference literature in the invention:
    > > > > "Programmable Logic Device Having Complex Logic Blocks with Improved
    > > > > Logic Cell Functionality", patent number 7,394,287, by Alera from
    > > > > following website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287...

    >
    > > > > Weng

    >
    > > > 7,394,287 is the patent number.  It works for me at the USPTO.  What
    > > > is the number you are searching for?

    >
    > > > Rick- Hide quoted text -

    >
    > > > - Show quoted text -

    >
    > > Hi Rick,
    > > I have tried to find the text and its drawings of patent application
    > > "Logic Cell
    > > Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US
    > > application number 10/718968, but it must pay to get its context from
    > > USPTO, even though it was in public domain about 6 years ago.

    >
    > > Can you help get the context and drawings from USPTO for me?

    >
    > > Weng

    >
    > Where did you get the above info?  That does not appear to be a valid
    > document number.  It needs to have 11 digits where the first four
    > appear to be the year.
    > I searched on "Three Binary Words" in the title and came up with
    > nothing.
    >
    > I did search on this for patents and found this one which I think is
    > interesting... maybe this is why the adder is just a plus sign with a
    > circle... 4,783,757.  Note that the owner is Intel, not Altera.
    >
    > Rick
    >
    > Rick- Hide quoted text -
    >
    > - Show quoted text -


    Hi Rick,
    I got the number from the patent "Programmable Logic Device Having
    Complex Logic Blocks with Improved Logic Cell Functionality"
    in its page 1 under "Other publications".
    http://www.google.com/patents/about...inm_is=0&as_miny_is=&as_maxm_is=0&as_maxy_is=

    Here is an email I sent to USPTO for confirmation and its response:
    Hi,
    I want to research patent application"Logic Cell Supporting Addition
    of Three Binary Words." U.S. Application Number 10/718,968, filed
    November 21, 2003.

    It should have been published long ago and in public domain.

    Please tell how to find the patent application.

    Thank you.

    Weng

    Hello

    The status of the application is
    93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF
    PUBLICATIONS.
    Thank you have a great day. Agent 31

    I don't know what it means.

    Weng
    Weng Tianxiang, Jun 16, 2009
    #17
  18. Re: About Altera patent application "Logic Cell Supporting Additionof Three Binary Words"

    On Jun 16, 7:02 pm, Chris Abele <> wrote:
    > Weng Tianxiang wrote:
    > > On Jun 16, 8:51 am, rickman <> wrote:
    > >> On Jun 16, 9:34 am, Weng Tianxiang <> wrote:

    >
    > >>> On Jun 15, 9:41 pm, rickman <> wrote:
    > >>>> On Jun 15, 1:39 pm, Weng Tianxiang <> wrote:
    > >>>>> On Jun 15, 9:23 am, OutputLogic <> wrote:
    > >>>>>> You can try to go to USPTO database and lookup the history of this
    > >>>>>> patent application.
    > >>>>>> It's not under the patent search, but under "http://www.uspto.gov" ->
    > >>>>>> "Patents" -> "view in PAIR" -> "public PAIR".
    > >>>>>> This database contains a complete history of the patent, including the
    > >>>>>> correspondence with patent examiners, etc.
    > >>>>>> Also, can you post the patent application number.
    > >>>>>> - outputlogic
    > >>>>>>http://outputlogic.com
    > >>>>> Hi OutputLogic,
    > >>>>> Thank you for your information.
    > >>>>> I had searched the website before I posed this message and got the
    > >>>>> error information:
    > >>>>> "Sorry, the entered Application Number "10/718968" is not available..
    > >>>>> The number may have been incorrectly typed, or assigned to an
    > >>>>> application
    > >>>>> that is not yet available for public inspection."
    > >>>>> I don't know why I got the error message.
    > >>>>> 10/718968 is available from reference literature in the invention:
    > >>>>> "Programmable Logic Device Having Complex Logic Blocks with Improved
    > >>>>> Logic Cell Functionality", patent number 7,394,287, by Alera from
    > >>>>> following website:http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287...
    > >>>>> Weng
    > >>>> 7,394,287 is the patent number.  It works for me at the USPTO.  What
    > >>>> is the number you are searching for?
    > >>>> Rick- Hide quoted text -
    > >>>> - Show quoted text -
    > >>> Hi Rick,
    > >>> I have tried to find the text and its drawings of patent application
    > >>> "Logic Cell
    > >>> Supporting Addition of Three Binary Words" filed on Nov. 21, 2003, US
    > >>> application number 10/718968, but it must pay to get its context from
    > >>> USPTO, even though it was in public domain about 6 years ago.
    > >>> Can you help get the context and drawings from USPTO for me?
    > >>> Weng
    > >> Where did you get the above info?  That does not appear to be a valid
    > >> document number.  It needs to have 11 digits where the first four
    > >> appear to be the year.
    > >> I searched on "Three Binary Words" in the title and came up with
    > >> nothing.

    >
    > >> I did search on this for patents and found this one which I think is
    > >> interesting... maybe this is why the adder is just a plus sign with a
    > >> circle... 4,783,757.  Note that the owner is Intel, not Altera.

    >
    > >> Rick

    >
    > >> Rick- Hide quoted text -

    >
    > >> - Show quoted text -

    >
    > > Hi Rick,
    > > I got the number from the patent "Programmable Logic Device Having
    > > Complex Logic Blocks with Improved Logic Cell Functionality"
    > > in its page 1 under "Other publications".
    > >http://www.google.com/patents/about?id=5yyrAAAAEBAJ&dq=patent:7394287...

    >
    > > Here is an email I sent to USPTO for confirmation and its response:
    > > Hi,
    > > I want to research patent application"Logic Cell Supporting Addition
    > > of Three Binary Words." U.S. Application Number 10/718,968, filed
    > > November 21, 2003.

    >
    > > It should have been published long ago and in public domain.

    >
    > > Please tell how to find the patent application.

    >
    > > Thank you.

    >
    > > Weng

    >
    > > Hello

    >
    > > The status of the application is
    > > 93 /NOTICE OF ALLOWANCE MAILED -- APPLICATION RECEIVED IN OFFICE OF
    > > PUBLICATIONS.
    > > Thank you have a great day. Agent 31

    >
    > > I don't know what it means.

    >
    > > Weng

    >
    > I'm confused: the Google page you linked to has a "Download PDF" button
    > which gets you the full 19 page patient.  There's also a link for "View
    > patient at USPTO" which takes you directly to the page for patient
    > number 7,394,287 at the USPTO site.  So what is it that you're looking for?
    >
    > Chris- Hide quoted text -
    >
    > - Show quoted text -


    Hi Chris,
    You have to download full patent papers to get the idea that the
    patent application "Logic Cell Supproting Addition of Three Binary
    Words" has not been approved for last 6.5 years.

    In the link I listed there is no the reference about the patent
    application. When you download the patent 7,394,287, in its page 1
    there is an item named "OTHER PUBLICATION". The first paper listed
    under the item is the patent application "Logic Cell Supproting
    Addition of Three Binary Words" which applied on November 21, 2003
    from where I've learned that the "Logic Cell Supproting Addition of
    Three Binary Words" has not been approved for last 6.5 years after I
    searched for the patent application name through USPTO patent website.

    Weng
    Weng Tianxiang, Jun 17, 2009
    #18
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