about hdl testbench

Discussion in 'VHDL' started by Neil, May 14, 2005.

  1. Neil

    Neil Guest

    Hi, All,
    I've written a hdl design, and simulate it now. But I can't find the
    way to write a hdl testbench to test the design. I've googled, But I
    can't find much material on net. could you give some advice or
    recommand some online material on this field so that I can get a
    general idea or deep knowledge on it? Thank you!

    //Neil
    Neil, May 14, 2005
    #1
    1. Advertising

  2. Neil wrote:


    > I've written a hdl design, and simulate it now. But I can't find the
    > way to write a hdl testbench to test the design.


    A testbench is nothing obscure. It is something you use to test your
    design. It depends on you how a test should be designed.

    Typically a testbench is a VHDL component that instantiates your design
    inside plus some additional components you need (e.g. a clock generator).

    Inside the testbench component you should generate some signals for your
    design. You are free how to do this (components, functions, procedures,
    synthesizable or not...). You may use the complete set of VHDL.


    > I've googled, But I
    > can't find much material on net.


    This is because a testbench is always specialized for one design and
    everybody writes testbenches a little bit different.



    Ralf
    Ralf Hildebrandt, May 14, 2005
    #2
    1. Advertising

  3. Neil wrote:

    > I've written a hdl design, and simulate it now. But I can't find the
    > way to write a hdl testbench to test the design.


    Step one is to install a vhdl simulator
    and run some tutorial examples.

    A testbench is a text file.
    It includes a null entity and
    architecture processes
    to wiggle and watch the design instance.

    Besides the UUT instance, I normally
    use a clock/reset generation process
    and a main process to wiggle and watch.

    Here's an example
    http://tinyurl.com/cv43m

    -- Mike Treseler
    Mike Treseler, May 14, 2005
    #3
  4. Neil

    Neil Guest

    Hi, Mike,
    Thank you first.
    I use Modelsim as my simulator, and now use waveform to simulate. but
    it seems not a good way when the design needs a long simulating time
    and the input signals are changed both regular and irregular.

    Let me read the sample first to get a general idea. thank you again.

    //Neil
    Neil, May 14, 2005
    #4
  5. Hi Neil,

    > I use Modelsim as my simulator, and now use waveform to simulate. but
    > it seems not a good way when the design needs a long simulating time
    > and the input signals are changed both regular and irregular.
    >
    > Let me read the sample first to get a general idea. thank you again.


    The attached three files might also be of interest. They follow roughly the
    same pattern but give you something to chew on. I wrote these on a Linux
    box, so you may not be able to open them properly with Notepad, but most
    other editors won't have any trouble with them.

    I find the use of the txt_util package most useful because you don't need to
    rely on ASSERT all the time.

    Best regards,


    Ben
    Ben Twijnstra, May 14, 2005
    #5
  6. Neil

    Andy Peters Guest

    Neil wrote:
    > Hi, All,
    > I've written a hdl design, and simulate it now. But I can't find the
    > way to write a hdl testbench to test the design. I've googled, But I
    > can't find much material on net. could you give some advice or
    > recommand some online material on this field so that I can get a
    > general idea or deep knowledge on it? Thank you!


    Start here:

    http://janick.bergeron.com/wtb/

    -a
    Andy Peters, May 16, 2005
    #6
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Kieran Francisco

    Timing Diagram to HDL Translation

    Kieran Francisco, Sep 8, 2003, in forum: VHDL
    Replies:
    9
    Views:
    1,289
    VhdlCohen
    Sep 17, 2003
  2. HDL Book Seller

    HDL books for sale

    HDL Book Seller, Sep 30, 2003, in forum: VHDL
    Replies:
    0
    Views:
    554
    HDL Book Seller
    Sep 30, 2003
  3. Alan
    Replies:
    0
    Views:
    521
  4. Guest

    X-HDL

    Guest, Nov 2, 2003, in forum: VHDL
    Replies:
    1
    Views:
    1,469
  5. Replies:
    0
    Views:
    786
Loading...

Share This Page