About process

Discussion in 'VHDL' started by mallu, Jul 5, 2006.

  1. mallu

    mallu Guest

    Hi, all

    I am newer to VHDL. I have a small design problem.
    I have two clocks and each one activate different process statements. I
    declared one variable in one process statement. But as per my design it
    should also modify in another process statement. To be clear How can i
    modify one variable or signal in two process statements.
     
    mallu, Jul 5, 2006
    #1
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  2. mallu

    KJ Guest

    mallu wrote:
    > Hi, all
    >
    > I am newer to VHDL. I have a small design problem.
    > I have two clocks and each one activate different process statements. I
    > declared one variable in one process statement. But as per my design it
    > should also modify in another process statement. To be clear How can i
    > modify one variable or signal in two process statements.


    Use a shared variable if it needs to be a variable, signals can be
    assigned within two processes.

    I'm betting that there's more that you'll find that you really need to
    figure out first before you can sucessfully do either approach, but
    based on the info you posted this is the answer.

    KJ
     
    KJ, Jul 5, 2006
    #2
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  3. mallu wrote:


    > I am newer to VHDL. I have a small design problem.
    > I have two clocks and each one activate different process statements. I
    > declared one variable in one process statement. But as per my design it
    > should also modify in another process statement. To be clear How can i
    > modify one variable or signal in two process statements.



    Simple answer: Don't do it if you want to write synthesizable code.

    You have to model some signal that is driven by the 2nd process and
    evaluated in the 1st one. This signal should show, that the variable has
    to be modified now.

    Think in terms of hardware. The state of one flipflop cannot be changed
    from two different and _independent_ drivers. You have to model some
    kind of handshaking. Maybe if the 2nd process sets an enable-signal
    active, then the flipflop of the 1st process has to sample a signal
    provided by the 2nd process, while otherwise it would sample a different
    signal.

    If you are really sure, that there is no way to model it this way a
    pseudo dual-edge flipflop may be an option. But I strongly recommend to
    think about a "normal" synchronous solution.


    Ralf
     
    Ralf Hildebrandt, Jul 5, 2006
    #3
  4. mallu

    john Guest

    Hi,
    Simplify your design as much as possible. Try to use only master clock.
    What are you trying to do ( application)?
    John
    mallu wrote:
    > Hi, all
    >
    > I am newer to VHDL. I have a small design problem.
    > I have two clocks and each one activate different process statements. I
    > declared one variable in one process statement. But as per my design it
    > should also modify in another process statement. To be clear How can i
    > modify one variable or signal in two process statements.
     
    john, Jul 5, 2006
    #4
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