About RAM

Discussion in 'VHDL' started by Okashii, Nov 29, 2005.

  1. Okashii

    Okashii Guest

    Hi there, I was reading the XST User Guide
    (http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/xst.pdf) and I came
    across examples of ram inference with vhdl. May I know whether ram are
    usually used for access to shared resources (like arrays in the those
    examples), or are there other uses for them?

    Also, if I want to read and write shared resources from different processes,
    should I be using a bus?
    Okashii, Nov 29, 2005
    #1
    1. Advertising

  2. Okashii wrote:

    > examples of ram inference with vhdl. May I know whether ram are
    > usually used for access to shared resources (like arrays in the those
    > examples), or are there other uses for them?


    RAM is a collection or registers that
    I can't wire to directly. The upside
    is that for most devices, a large RAM array
    is much more efficient that a large register array.
    FPGA block ram is commonly used for hash/trigger tables,
    fifos and other data buffers.

    > Also, if I want to read and write shared resources from different processes,
    > should I be using a bus?


    I like to minimize shared resources.
    If they are needed, I wrap a server
    entity around them and interface with
    synchronous data and ready/ack handshakes.

    top entity: [device pins]
    |
    top signals: handshake_signals port_maps
    | | | | |
    design entities: [server][client][mixed][direct]


    -- Mike Treseler
    Mike Treseler, Nov 29, 2005
    #2
    1. Advertising

  3. Okashii

    Andy Peters Guest

    Okashii wrote:
    > Hi there, I was reading the XST User Guide
    > (http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/xst.pdf) and I came
    > across examples of ram inference with vhdl. May I know whether ram are
    > usually used for access to shared resources (like arrays in the those
    > examples), or are there other uses for them?


    Well, I suppose one could use RAM wherever one needed to store data.

    The one downside of RAM, as compared to building registers out of
    flip-flops, is that you need to supply an address to read the RAM. In
    other words, all data stored in the RAM are not immediately available.
    A register output of course is always available.

    > Also, if I want to read and write shared resources from different processes,
    > should I be using a bus?


    I suppose so ... I can't think of any other mechanism ...

    -a
    Andy Peters, Nov 29, 2005
    #3
  4. Okashii

    Andy Guest

    Okashii wrote:
    > Hi there, I was reading the XST User Guide
    > (http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/xst.pdf) and I came
    > across examples of ram inference with vhdl. May I know whether ram are
    > usually used for access to shared resources (like arrays in the those
    > examples), or are there other uses for them?
    >
    > Also, if I want to read and write shared resources from different processes,
    > should I be using a bus?


    Here is an excellent article on using ram in fpga logic design:

    http://www.xilinx.com/xlnx/xweb/xil...uageID=1&multPartNum=1&sTechX_ID=kc_perf_time

    In case that does not work, search for "Performance + Time = Memory" on
    xilinx's website.

    Think of it as time division multiplexing multiple channels with the
    same combinatorial logic, and using ram instead of flops for all your
    storage. A simple counter sequences through the memory addresses so
    each channel gets processed, one at a time. I've used this in the past
    with excellent results, in regards to both performance and utilization.

    Andy
    Andy, Dec 1, 2005
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Pieter Hulshoff
    Replies:
    0
    Views:
    1,042
    Pieter Hulshoff
    Aug 13, 2003
  2. Robert Posey
    Replies:
    0
    Views:
    668
    Robert Posey
    Nov 26, 2003
  3. ashu
    Replies:
    1
    Views:
    454
  4. ashu
    Replies:
    2
    Views:
    608
    mysticlol
    Nov 6, 2006
  5. Xin Xiao

    Block RAM Distributed RAM

    Xin Xiao, Jan 7, 2008, in forum: VHDL
    Replies:
    8
    Views:
    1,463
    Duane Clark
    Jan 7, 2008
Loading...

Share This Page