about "super state machine"

Discussion in 'VHDL' started by Neil, May 3, 2005.

  1. Neil

    Neil Guest

    super state machine, I've google it, and find there isn't enough
    entries to explain it, and I can't get the general idea about it.

    what's the form of it? can anyone help to explain it?

    thanks!
     
    Neil, May 3, 2005
    #1
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