About the values in VHDL std_logic_vector

Discussion in 'VHDL' started by parag_paul@hotmail.com, Sep 14, 2007.

  1. Guest

    The std logic package has some values defined as follows,

    U unitialized
    X forcing unknown
    1 forcing 1
    0 forcing 0
    L weak 0
    H Weak 1

    Now, does a assign like
    a:= 1
    mean that it has been forced a value of 1. Is that correct , Does it
    mean it will hold , until another, assign happens.
    , Sep 14, 2007
    #1
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  2. Andy Guest

    On Sep 14, 2:01 pm, "" <>
    wrote:
    > The std logic package has some values defined as follows,
    >
    > U unitialized
    > X forcing unknown
    > 1 forcing 1
    > 0 forcing 0
    > L weak 0
    > H Weak 1
    >
    > Now, does a assign like
    > a:= 1
    > mean that it has been forced a value of 1. Is that correct , Does it
    > mean it will hold , until another, assign happens.


    >From your syntax, "a" must be an integer type variable. 1 is a number

    (integer). '1' is logic high in std_logic system.

    VHDL variables operate just like variables in other languages;
    assignments to them are in force until another assignment to the same
    variable is executed.

    If on the other hand, you meant to say:

    a <= '1';

    then we have a signal assignment.

    If the assignment appears outside of a process or subprogram, then it
    is a concurrent assignment, and creates a driver, with a constant
    value of '1', continually driving your signal.

    If the assignment appears inside a process, then it is a sequential
    assignment. Only one driver is created for that process, regardless of
    how many assignments are made within the process. Only the last
    executed assignment prior to the process suspending is used. Updates
    take effect when the process suspends (i.e. waiting for another event,
    etc.).

    If multiple processes and/or concurrent assignment statements drive
    the same signal, the effective value for the signal must be resolved
    from all of the drivers. There are no "forcing" values in the
    std_logic system: drivers with '1' and '0' on the same signal will
    result in an 'X', etc.

    Andy
    Andy, Sep 14, 2007
    #2
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  3. Guest

    Is there a forcing value system in VHDL itself. I mean something like
    force and release in verilog.

    I was confused with the definitions of 1 and 0 and though , H and L
    are the appropriate ones.

    Other than the std_logic what are the other value systems available in
    VHDL
    , Sep 15, 2007
    #3
  4. On Fri, 14 Sep 2007 22:38:45 -0700, ""
    <> wrote:

    >Is there a forcing value system in VHDL itself. I mean something like
    >force and release in verilog.


    Not in the language, no. Simulators usually provide the
    force functionality.

    It would be possible to invent a new resolution function for
    std_ulogic (or any other data type) providing a "forcing"
    value, but you need to be aware that simulators are highly
    optimized for the standard implementation of std_logic and
    any change to it would drastically worsen simulator performance.
    Synthesis tools generally do not support any kind of non-standard
    resolution function.

    >I was confused with the definitions of 1 and 0 and though , H and L
    >are the appropriate ones.


    For what?

    >Other than the std_logic what are the other value systems available in
    >VHDL


    Any that you care to write. There are built-in data types for
    boolean (FALSE, TRUE) and bit ('0', '1'). Others you would need
    to write for yourself.
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Sep 15, 2007
    #4
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