about VHDL deltas

Discussion in 'VHDL' started by parag_paul@hotmail.com, Dec 10, 2007.

  1. Guest

    HI all,
    is there a concept of deltas in VHDL ,

    I am implementing something like the force command in Verilog in VHDL

    Now is it ok that there is a delta before the forced value gets
    reflected on the signal.

    Something like the following in UCLI ( Synopsys debug tool for VCS)

    ucli% force a 1
    ucli% get a
    0
    ucli% run 1 us
    ucli% get a
    1
    ucli%


    here , actually, the force value did not reflect immediately but we
    have to wait for some delta to get there.
    IS the acceptable, or is the concept not viable in VHDL> IN Verilog we
    are seeing the value reflection immediately
    Thanks in advance
    -Parag
    , Dec 10, 2007
    #1
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  2. KJ Guest

    On Dec 10, 5:29 am, "" <>
    wrote:
    > HI all,
    > is there a concept of deltas in VHDL ,
    >
    > I am implementing something like the force command in Verilog in VHDL
    >
    > Now is it ok that there is a delta before the forced value gets
    > reflected on the signal.
    >
    > Something like the following in UCLI ( Synopsys debug tool for VCS)
    >
    > ucli% force a 1
    > ucli% get a
    > 0
    > ucli% run 1 us
    > ucli% get a
    > 1
    > ucli%
    >
    > here , actually, the force value did not reflect immediately but we
    > have to wait for some delta to get there.
    > IS the acceptable, or is the concept not viable in VHDL> IN Verilog we
    > are seeing the value reflection immediately
    > Thanks in advance
    > -Parag


    What you're asking about has nothing to do with VHDL or Verilog, it is
    specific to whatever simulation tool you're using...and yes, probably
    every simulation tool in existence that has a user interface will
    allow you to force signals and they will most likely show up on the
    next simulation delta.

    KJ
    KJ, Dec 10, 2007
    #2
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  3. On 10 Dez., 11:29, wrote:
    > is there a concept of deltas in VHDL ,


    Yes, signals use delta (or often called ticks) to update, variables
    are immediate updated.
    Hence:
    A_Sig <= '1';
    A_Var := '1';
    wait 1 ns;
    A_Sig <= '0';
    A_Var := '0';
    A_Sig <= A_Var;
    A_Var := A_Sig;
    wait 1 ns;

    lead to:
    A_Sig = '0'
    A_Var = '1'

    bye Thomas
    Thomas Stanka, Dec 11, 2007
    #3
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