about xilinx synthesizer.

Discussion in 'VHDL' started by Amit, Nov 2, 2008.

  1. Amit

    Amit Guest

    hello group,

    I have written two small vhdl code and now I am asked the following
    questions, please just point where I can find some reading about it to
    answer them. (I am using xilinx ise)

    regards,
    amit


    Different synthesis tools use different styles to synthesize the state
    machines.
    Whatstyle does XST use to synthesize the state machine that you
    coded?
    Is there any way to force the tool to use specific options for
    synthesizing state machines?
    Amit, Nov 2, 2008
    #1
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  2. Amit wrote:

    > I have written two small vhdl code and now I am asked the following
    > questions, please just point where I can find some reading about it to
    > answer them. (I am using xilinx ise)


    > Different synthesis tools use different styles to synthesize the state
    > machines. What style does XST use to synthesize the state machine that you
    > coded? Is there any way to force the tool to use specific options for
    > synthesizing state machines?


    It is unfortunate that your instructor would ask
    such a poorly formed question.
    A register that is declared as a type enumeration
    has no explicit encoding. For example, a register
    of the type

    type TxState_t is (
    IDLE,
    START,
    SEND,
    STOP
    );

    is usually encoded using the binary values of two flops,
    or onehot values of four flops. If the designer gives
    no further hints, synthesis will use its default
    encoding strategy. This strategy will vary by vendor,
    target device, and tool version.

    Last time I checked, brands A and X use binary
    encoding up to enum length 4 and one-hot encoding
    for larger enums. This is a synthesis optimization
    and in 99.9% of cases the designer saves time
    and gets adequate utilization by using the defaults.

    Old school TTL and verilog designs did not have
    the option of the enum abstraction, and many
    academics remain fascinated by the notion
    of an 'optimum' state encoding.

    No worse than playing tetris, or working
    crossword puzzles, I suppose.

    -- Mike Treseler
    Mike Treseler, Nov 2, 2008
    #2
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  3. Amit

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Well I'm an instructor :) and could have asked this question myself.

    The correct answer will properly be:

    If your implement a statemachine in a CPLD will the combinatorial logic compared with the number of F/Fs mean that binary and gray style gives the best implementation.

    If how ever your coding for a FPGA will the number of F/F's be quite large and hence will a One hot coding give the best result. This specially true if you want to implement a statemachine with more then say 20 states.

    BUT for a 5 states State Machine would it be hard to spot any diffence in the number af LUTs used.

    If you right click at the Synthesize menu can you find a selection for the statemachine coding (See below)

    Hope you found this useful
    Jeppe

    [​IMG]
    Last edited: Nov 2, 2008
    jeppe, Nov 2, 2008
    #3
  4. Amit

    Enes Erdin Guest

    You can read Xilinx constraints guide. Here you will see that there is
    an attribute called FSM_STYLE. By this you can force "XST" to use a
    defined way of encoding. Or you can do it through synthesis options in
    "XST".

    I think this helps you.

    Good luck,

    --enes
    Enes Erdin, Nov 3, 2008
    #4
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