access function from outside

Discussion in 'VHDL' started by Torsten Bitterlich, Jul 6, 2003.

  1. Hi there,

    what I want to do is to implement a function or procedure within a
    entity, which can be accessed from the outside of the belonging entity.
    I need this to get some status information at the end of the simulation
    out of a component. Since the component doesn't know about the end of
    the simulation, the testbench should access this function to do the
    task. Is this possible with VHDL or is there a clean way to implement
    this behaviour?

    Thanks for any help,

    Torsten Bitterlich
     
    Torsten Bitterlich, Jul 6, 2003
    #1
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  2. Torsten Bitterlich

    Alan Fitch Guest

    >
    > what I want to do is to implement a function or procedure

    within a
    > entity, which can be accessed from the outside of the

    belonging entity.
    > I need this to get some status information at the end of

    the simulation
    > out of a component. Since the component doesn't know about

    the end of
    > the simulation, the testbench should access this function

    to do the
    > task. Is this possible with VHDL or is there a clean way

    to implement
    > this behaviour?


    If you want to do this in "pure VHDL", then you can put
    signals
    in a package. These signals can then be made visible
    anywhere
    in your design by making the package visible in a particular
    design entity.

    For instance,

    package probe is

    signal SimDone : STD_LOGIC;

    end package probe;


    entity TestBench

    end entity TestBench;

    architecture A of TestBench is


    begin

    stim: process
    begin
    -- do lots of stuff

    SimDone <= '0';
    wait for 1 ns;
    SimDone <= '1';
    wait for 1 ns ;

    wait;
    end process;


    ...

    end architecture A;


    -- synopsys translate_on
    use WORK.probe;
    -- synopsys translate_on
    entity Design

    end entity Design;

    architecture RTL of Design
    begin

    -- synopsys translate_off
    Monitor: process

    begin
    wait until rising_edge(probe.SimDone);

    -- e.g. write stuff to a file
    end process;


    -- synopsys translate_on

    ... rest of design


    end architecture RTL;


    =========================================
    You could also of course add a port, but that's more
    tedious as you have to propagate it up the hierarchy.

    You can also "cheat". Most simulators nowadays use
    Tcl/Tk so you could use a Tcl routine in the simulator.

    Alternatively, some simulators allow access to signals
    via the foreign language interface (for instance the
    Modelsim SignalSpy).

    However signals in a package are at least pure VHDL!

    kind regards

    Alan




    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
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    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
    Hampshire, BH24 1AW, UK
    Tel: +44 (0)1425 471223 mail:

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    The contents of this message may contain personal views
    which are not the
    views of Doulos Ltd., unless specifically stated.
     
    Alan Fitch, Jul 7, 2003
    #2
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