access internal signal in VHDL from verilog

[tkvhdl]

Hi,
I've been using signal_spy and nc_mirror to access signals from one
VHDL block to a verilog block. However, I noticed that nc_mirror does
not handle custom types or types like signed, unsigned, etc. I even
have an issue with a std_logic_vector if it is part of a record. I
realize it is only supported for std_logic/std_logic_vector, however,
modelsim doesn't have issues for some of these cases.
Is there a simulator independant way of doing this in VHDL-200x that
also works across languages?

 

[Mike Treseler]

I've been using signal_spy and nc_mirror to access signals from one
VHDL block to a verilog block. However, I noticed that nc_mirror does
not handle custom types or types like signed, unsigned, etc. I even
have an issue with a std_logic_vector if it is part of a record. I
realize it is only supported for std_logic/std_logic_vector, however,
modelsim doesn't have issues for some of these cases.
Is there a simulator independant way of doing this in VHDL-200x that
also works across languages?

testpoint ports?

You mentioned signal_spy.
What's wrong with that?


-- Mike Treseler

 

[tkvhdl]

testpoint ports?

You mentioned signal_spy.
What's wrong with that?

-- Mike Treseler

It's not simulator independant

 

[Jonathan Bromley]

On Wed, 27 Jun 2007 17:25:37 -0000,

[Mike Treseler]

You mentioned signal_spy.
What's wrong with that?

[tkvhdl]
It's not simulator independant

Nor will anything else be, until the newly-ratified
VHPI spec is fully implemented by all major vendors.

All the major tool vendors will allow you to use
SystemVerilog's "bind" construct to insert an instance
of a Verilog module at any point in the design
hierarchy. That might provide a good alternative,
since the bound module can have its ports connected to
any signals you choose at the point where it's bound.

Plenty of people are already using "bind" to insert
modules full of SystemVerilog assertions into a
VHDL design, for example. Coverage collection
using SystemVerilog covergroups is another "sweet
spot" for this approach.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[tkvhdl]

On Wed, 27 Jun 2007 17:25:37 -0000,


[Mike Treseler]

You mentioned signal_spy.
What's wrong with that?

[tkvhdl]

It's not simulator independant

Nor will anything else be, until the newly-ratified
VHPI spec is fully implemented by all major vendors.

All the major tool vendors will allow you to use
SystemVerilog's "bind" construct to insert an instance
of a Verilog module at any point in the design
hierarchy. That might provide a good alternative,
since the bound module can have its ports connected to
any signals you choose at the point where it's bound.

Plenty of people are already using "bind" to insert
modules full of SystemVerilog assertions into a
VHDL design, for example. Coverage collection
using SystemVerilog covergroups is another "sweet
spot" for this approach.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks, I'll look into this.