access internal signal on top level in VHDL

Discussion in 'VHDL' started by anupam, Jan 27, 2006.

  1. anupam

    anupam Guest

    hi,
    i want to force a value or read a value of an internal signal in VHDL .
    That is possible with signal spy in model sim but i want to use ncsim .
    Is it possible with ncsim without using any other language's interface
    (like c or tcl)??
    please suggest
     
    anupam, Jan 27, 2006
    #1
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  2. anupam

    Ajeetha Guest

    NC has similar feature called NC_MIRROR. You may also want to look at a
    small package that we wrote a while back to work seamlessly across
    simulators. I'm updating ti for VCSMX soon, but the one that works with
    MTI/NC/Aldec is @

    http://www.noveldv.com/eda/probe.zip

    HTH
    Ajeetha
    www.noveldv.com
     
    Ajeetha, Jan 27, 2006
    #2
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  3. Ralf Hildebrandt, Jan 27, 2006
    #3
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