Access order and LE reduction in FORTH chip

Discussion in 'VHDL' started by jacko, Jul 18, 2007.

  1. jacko

    jacko Guest

    hi

    would i be correct in the assumption that i could get a lower logic
    complexity, and faster speed on http://indi.hpsdr.com processor if i
    changed the fetch execute order with an 8 bit mem interface to only
    load the instruction register with 8 bits, and removed the high/low
    byte multiplexer which follows the current 16 bit instruction
    register?

    i.e lose 8 flip flops and 16 and gates and one inverter. This does
    however change the execution semantics if the MSB opcode modifies the
    p register, to a jump and execute LSB instruction. And would need some
    repacking of 16bit code when moving to 32bit code (not very difficult
    but not 100% compatible with lowest logic count unless some kind of
    byte interleave used).

    cheers

    jacko
     
    jacko, Jul 18, 2007
    #1
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