Access order and LE reduction in FORTH chip

Discussion in 'VHDL' started by jacko, Jul 18, 2007.

  1. jacko

    jacko Guest

    hi

    would i be correct in the assumption that i could get a lower logic
    complexity, and faster speed on http://indi.hpsdr.com processor if i
    changed the fetch execute order with an 8 bit mem interface to only
    load the instruction register with 8 bits, and removed the high/low
    byte multiplexer which follows the current 16 bit instruction
    register?

    i.e lose 8 flip flops and 16 and gates and one inverter. This does
    however change the execution semantics if the MSB opcode modifies the
    p register, to a jump and execute LSB instruction. And would need some
    repacking of 16bit code when moving to 32bit code (not very difficult
    but not 100% compatible with lowest logic count unless some kind of
    byte interleave used).

    cheers

    jacko
     
    jacko, Jul 18, 2007
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. John Benson
    Replies:
    4
    Views:
    733
    David M. Cooke
    Jan 9, 2004
  2. Jeffrey Walton

    Division and Modular Reduction

    Jeffrey Walton, Jul 29, 2011, in forum: C++
    Replies:
    1
    Views:
    391
    Victor Bazarov
    Jul 29, 2011
  3. Jeffrey Walton

    Division and Modular Reduction (Repost)

    Jeffrey Walton, Jul 29, 2011, in forum: C++
    Replies:
    0
    Views:
    217
    Jeffrey Walton
    Jul 29, 2011
  4. jason
    Replies:
    3
    Views:
    143
    jason
    Aug 14, 2003
  5. jason
    Replies:
    0
    Views:
    117
    jason
    Aug 14, 2003
Loading...

Share This Page