Access to signals inside an entity

[Thomas Fuchs]

Hi,
I want to access signals of my entity under test from my testbench. Is
it possible? I need it for writing the data into a "Data.txt" file.
I don't want to change the vhdl file of my test entity.
I use modelsim for simulation and I didn't find a way to do it.
Thanks.

Thomas

 

[Tim Hubberstey]

Hi,
I want to access signals of my entity under test from my testbench. Is
it possible?

No. VHDL does not support direct access to signals inside another entity.

I need it for writing the data into a "Data.txt" file.
I don't want to change the vhdl file of my test entity.
I use modelsim for simulation and I didn't find a way to do it.

ModelSim has access to all signals and variables throughout your design.
You can use the Tcl features of ModelSim to look inside other entities
and pass signals back to your testbench. There is a considerable
simulation speed penalty for doing this.

You do this by having a Tcl script (.do file) watch for a particular
condition on the signal(s) of interest (wherever they are in the design)
and then 'force' a value onto a port or signal in your testbench. I
suggest you read up on the 'when' command in the ModelSim command
reference manual.

 

[Paul Uiterlinden]

No. VHDL does not support direct access to signals inside another
entity.

Not directly. But see the FAQ:
http://www.eda.org/comp.lang.vhdl/FAQ1.html#monitor

ModelSim has access to all signals and variables throughout your
design. You can use the Tcl features of ModelSim to look inside
other entities and pass signals back to your testbench.

See also:
http://www.model.com/support/technotes/simulation/probe_and_force_with_signal_spy.pdf

Paul.