Adding an output register to a lookahead FIFO

Discussion in 'VHDL' started by cmkastn, Mar 22, 2010.

  1. cmkastn

    cmkastn

    Joined:
    Mar 22, 2010
    Messages:
    1
    I'm implementing an Altera lookahead FIFO here, and I'm not making timing... so I'm adding another output register to the FIFO to see if that will do the trick.

    However, I get a glitch on the rd_int signal during some situations. Could anyone tell me if I'm doing something incorrect here?

    Code:
    entity fifo_1clk is
    
      generic (
        addr_width :     natural := 8;
        data_width :     natural := 8
        );
      port
        (
          aclr     : in  std_logic;
          clock    : in  std_logic;
          data     : in  std_logic_vector (data_width-1 downto 0);
          rdreq    : in  std_logic;
          wrreq    : in  std_logic;
          empty    : out std_logic;
          full     : out std_logic;
          q        : out std_logic_vector (data_width-1 downto 0);
          usedw    : OUT STD_LOGIC_VECTOR (addr_width-1 downto 0)
          );
    END fifo_1clk;
    Code:
            signal rdreq_int : std_logic;
            signal empty_int : std_logic;
            signal q_int     : std_logic_vector(data_width-1 downto 0);
            signal q_valid   : std_logic;
    Code:
            scfifo_inst : scfifo
              port map (
                  aclr         => aclr,
                  almost_empty => open,
                  almost_full  => open,
                  clock        => clock,
                  data         => data,
                  empty        => empty_int,
                  full         => full,
                  q            => q_int,
                  rdreq        => rdreq_int,
                  sclr         => '0',
                  usedw        => usedw,
                  wrreq        => wrreq
                  );
    
            empty <= (not q_valid);
            rdreq_int <= (not empty_int and not q_valid) or (not empty_int and q_valid and rdreq);
    
            register_outputs : process(clock, aclr)
            begin
              if aclr = '1' then
                q_valid <= '0';
              elsif clock'event and clock = '1' then
                if q_valid = '0' then
                  q_valid <= (not empty_int);
                  q       <= q_int;
                elsif rdreq = '1' then
                  q_valid <= (not empty_int);
                  q       <= q_int;
                end if;
              end if;
            end process;
    cmkastn, Mar 22, 2010
    #1
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