Adding signals of different size

Discussion in 'VHDL' started by abidbodal, Jun 29, 2009.

  1. abidbodal

    abidbodal

    Joined:
    Jun 29, 2009
    Messages:
    2
    Can you add two signals and assign them to another signal of a different size?

    Here's part of my code:

    signal sv16_wh1_0_cnt :std_logic_vector (15 downto 0);
    signal sv16_wh1_90_cnt :std_logic_vector (15 downto 0);
    signal sv17_wh1_aver :std_logic_vector (16 downto 0);

    --this takes place in a clocked process
    sv17_wh1_aver <= (sv16_wh1_0_cnt + sv16_wh1_90_cnt) ;
    abidbodal, Jun 29, 2009
    #1
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  2. abidbodal

    jeppe

    Joined:
    Mar 10, 2008
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    Denmark
    Try this:

    sv17_wh1_aver <= ('0'&sv16_wh1_0_cnt + '0'&sv16_wh1_90_cnt)

    You might be forced to use temp variable of the size 16 downto 0
    jeppe, Jun 29, 2009
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  3. abidbodal

    abidbodal

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    Jun 29, 2009
    Messages:
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    Thanks, that worked
    abidbodal, Jul 1, 2009
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