adding std_logic_vectors in vhdl

Discussion in 'VHDL' started by ohaqqi, Oct 17, 2006.

  1. ohaqqi

    ohaqqi

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    Oct 15, 2006
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    For a command like this one:

    C <= std_logic_vector(signed(A) + signed(B))

    How does VHDL add the vectors? For example, If I wanted to synthesize this on an FPGA, would the compiler create an adder? Or does it use some other technique to add vectors?
    Sorry if this is too much of a newbie question :)
     
    ohaqqi, Oct 17, 2006
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  2. ohaqqi

    zty

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    i think the synthesis tool will add many adder depend on the length of your vector.


     
    zty, Oct 17, 2006
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  3. ohaqqi

    ohaqqi

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    That makes sense, thanks.

    Does it use ripple-carry or carry-look-ahead adders?
     
    ohaqqi, Oct 17, 2006
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  4. ohaqqi

    Daniel Kho

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    Different compilers synthesize the same code differently sometimes. I guess you can know how your particular FPGA would implement your code at the RTL level by looking at the RTL viewer if your vendor provides such an option.
     
    Daniel Kho, Oct 18, 2006
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