Nicolas and Paul,
Maybe I am not an advanced user enough but I can't see
what's missing in numeric_std that would need the
addition of a new package.
First considering testbenches. If you have a design
where you want to apply an algorithm on an address,
you need to do unsigned math. Most ports of designs
are std_logic_vector (due to limitations of some
synthesis tools). Hence to do this, you can:
1) Use std_logic_unsigned/numeric_unsigned and
just do it.
2) Use all unsigned signals and convert them to
std_logic_vector at the instantiation.
3) Use std_logic_vector signals and do lots of
type casting.
I commonly do 1, but have been contemplating doing 2.
-------------------
For RTL design, all math should be done with numeric_std.
However, is an incrementer really math - do I really
need a type to convey what I am doing?
All implicit comparisons in VHDL are done using a
lexigraphic sort (dictionary ordering). If you are
doing comparisons, it is much safer to use a math
package (either numeric_std or the future numeric_unsigned).
For the following std_logic_vector comparisons, which
is more readable:
-- with only 1164
Y <= '1' when A = "1010" else '0' ;
-- with numeric_unsigned/std_logic_unsigned
Y <= '1' when A = 10 else '0' ;
-- with numeric_std:
Y <= '1' when unsigned(A) = 10 else '0' ;
Going further what if A increases by 1 bit, but
your forget to update your literal above?
With just std_logic_1164, the first one is still
legal, but it will not produce what you want.
With the std_logic_unsigned or the future
numeric_unsigned, both forms are still correct.
-------------------
From Paul:
Though this was convenient, it is actually not allowed to overload an
operator (e.g. "=") in another package (std_logic_unsigned) than where
it originally was defined (std_logic_1164, which impicitely defines an
"=" operator with the declaration of the std_logic type). Hence the
"-explicit" option in ModelSim to allow the non LRM compliant code.
This is being corrected. In the next rev of the LRM, explicit
operators will always override implicit operators. In fact, you
will notice that ModelSim now makes the explicit flag set by default.
Where we have the flexability and it does not sacrafice
correctness or the spirit of VHDL, we should give people
the ability to adopt their own methodology. The great
thing about this being a package is that if you like
a methodology that uses only numeric_std, then don't
include the other package and life is good.
Cheers,
Jim
P.S.
Note there are _no_ plans to create a numeric_signed.
--
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Jim Lewis
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SynthWorks Design Inc.
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Expert VHDL Training for Hardware Design and Verification
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