Address Decoding Logic

Discussion in 'VHDL' started by Kantha, Jun 6, 2006.

  1. Kantha

    Kantha Guest

    Hi all,
    I am slightly confused about which type of address decoding logic
    should be used when?.
    Consider an example where I need to write and read back some 50
    registers in FPGA from a host processor.
    Consider,
    S_Write_Enable <= write_from_cpu or Ce ;
    -- /AWE(Write enable) or /CE(chip enable(Active low))
    S_Read_Enable <= read_from_cpu or Ce;
    -- /ARE(Read enable) or /CE(chip enable(Active low))
    I first tried to use the Case logic,as I needed to program 4 channel
    parameters, which could be easily written using Case logic.
    Process(S_Write_Enable,Reset)
    variable Vl_Offset := std_logic_vector(3 downto 0);
    variable Vl_ch_num := std_logic_vector(1 downto 0);
    begin
    if(Reset = '1') then
    -- initializatin
    elsif(S_Write_Enable'event AND S_Write_Enable = '0') then
    Vl_Offset := address_input(3 downto 0);
    Vl_ch_num := conv_integer(address_input(5 downto 4));
    case Vl_Offset is
    when ZERO =>
    S_Ch_Control_Reg <= data_bus;
    when ONE =>
    S_Code_Phase_Inc(Vl_ch_num)(31 downto 16) <= data_bus;
    when TWO =>
    S_Code_Phase_Inc(Vl_ch_num)(15 downto 0) <= data_bus;
    when THREE =>
    S_Data_Phase_Inc(Vl_ch_num)(31 downto 16) <= data_bus;
    when FOUR =>
    S_Data_Phase_Inc(Vl_ch_num)(15 downto 0) <= data_bus;
    -
    - Other decoding logics-- 15 * 4 registers(4 Channel Parameters)
    -
    when others => null;
    end case;
    end if;
    end process;
    While reading the registers also , I used the same decoding logic to
    read back the registers.
    I dont know why? i got timing errors i.e when I simulated it using
    ModelSim 5.3 ., and programmed setup(/CE low to AWE low) as 30ns ,
    strobe time(/AWE low time) as 30 ns and hold time(/AWE high to /CE
    high) as 30 ns. The registers were in unknown state.
    How does the case logic works? does it do priority encoding or normal
    encoding??
    I changed my case logic to direct if-else structure which worked fine .
    But I still dont understand why the same logic didnot work in Case.
    Process(S_Write_Enable,Reset)
    variable Vl_Offset := std_logic_vector(3 downto 0);
    variable Vl_ch_num := std_logic_vector(1 downto 0);
    begin
    if(Reset = '1') then
    -- initializatin
    elsif(S_Write_Enable'event AND S_Write_Enable = '0') then
    if(address_input = "0000001000") then
    S_Code_Aid1(0) <= data_bus(C_LFSR_LENGTH-1 downto 0);
    end if;
    if(address_input = "0000001001") then
    S_Code_Aid2(0) <= data_bus(C_LFSR_LENGTH-1 downto 0);
    end if;
    if(address_input = "0000011000") then
    S_Code_Aid1(1) <= data_bus(C_LFSR_LENGTH-1 downto 0);
    end if;
    if(address_input = "0000011001") then
    S_Code_Aid2(1) <= data_bus(C_LFSR_LENGTH-1 downto 0);
    end if;
    if(address_input = X"0028") then
    S_Code_Aid1(2) <= data_bus(C_LFSR_LENGTH-1 downto 0);
    end if
    if(address_input = X"0029") then
    S_Code_Aid2(2) <= data_bus(C_LFSR_LENGTH-1 downto 0);
    end if;
    end if;
    Kantha, Jun 6, 2006
    #1
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Laurent Pinchart

    Address decoding

    Laurent Pinchart, Apr 11, 2004, in forum: VHDL
    Replies:
    3
    Views:
    6,307
    Jim Lewis
    Apr 12, 2004
  2. avnrao
    Replies:
    1
    Views:
    7,206
    avnrao
    May 4, 2004
  3. Patrice
    Replies:
    0
    Views:
    876
    Patrice
    May 4, 2004
  4. Srikanth

    Address Decoding Logic

    Srikanth, Jun 6, 2006, in forum: VHDL
    Replies:
    0
    Views:
    643
    Srikanth
    Jun 6, 2006
  5. spike
    Replies:
    8
    Views:
    1,435
    Steve Holden
    Feb 9, 2010
Loading...

Share This Page