After Place and Route

Discussion in 'VHDL' started by ec, Jan 2, 2007.

  1. ec

    ec Guest

    Hi

    What if after Place and Route the timing constarint are lower then needed ,
    what should be done ?

    Should I generate another netlist , or should I try to change the VHDL code
    of the model
    and then to generate a new netlist and > new place and route ?

    Thanks in advace
    EC
    ec, Jan 2, 2007
    #1
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  2. ec wrote:

    > What if after Place and Route the timing constarint are lower then needed ,
    > what should be done ?


    Your choices are
    1. Reduce the clock frequency.
    2. Pipeline the design.
    3. Use a faster device.

    -- Mike Treseler
    Mike Treseler, Jan 2, 2007
    #2
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  3. Mike Treseler schrieb:

    > ec wrote:
    >
    > > What if after Place and Route the timing constarint are lower then needed ,
    > > what should be done ?


    First you should analyse the longest paths to have an idea why your
    design miss your contraints. This could help you a lot in deceiding
    what to do next.

    > Your choices are
    > 1. Reduce the clock frequency.
    > 2. Pipeline the design.
    > 3. Use a faster device.


    2a) instead of real pipelining it is often possible to gain speed by
    simple changes of your HW structure (eg. change state encoding, use
    resource doubbling to improve timing, use downto-0 counter or lfsr
    instead of up-to-constant counter,...). For complex fsm you _could_
    gain a lot with major reworking if your first fsm design leads to high
    fanout nets.

    4. for slight violations you could
    a) change the P&R until it fits (preplacing by hand can help a lot,
    but don't expect miracles)
    b) change the environmetal parameters if applicabel (e.g if your
    voltage is in every case much better than worst case, you could
    increase voltage for worst case timing analyses (if your tool allows to
    do so))

    5. rerun synthesis with other timing constraints (can help in _some_
    cases, sometimes you can gain even with loose contraints)

    6. Flatten Netlist, if it is still hierachically and your tool has some
    weaknesses on module bounds.

    4 -6 can do for up to ~30% depending on your design. If you want 100Mhz
    and even miss 50 Mhz you typically need to use choices 1-3.

    bye Thomas
    Thomas Stanka, Jan 3, 2007
    #3
  4. ec

    ec Guest

    Thanks
    ec

    "Mike Treseler" <> ???
    ??????:...
    > ec wrote:
    >
    >> What if after Place and Route the timing constarint are lower then needed
    >> ,
    >> what should be done ?

    >
    > Your choices are
    > 1. Reduce the clock frequency.
    > 2. Pipeline the design.
    > 3. Use a faster device.
    >
    > -- Mike Treseler
    ec, Jan 3, 2007
    #4
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