again on state machine

Discussion in 'VHDL' started by Max, Sep 10, 2003.

  1. Max

    Max Guest

    I need that my state machine starts on rising_edge of a signal, then
    it must be synchronous with clk. When the last state has been
    executed, I must wait a rising_edge again:

    I wrote this:

    architecture Behavioral of main is
    type state_type is (ST0, ST1, ST2, ST3);
    signal state: state_type;

    begin

    process (clk, start, reset)
    begin
    if reset = '1' then
    state <= st0;
    elsif (rising_edge(start) and state = st0) then
    state <= st1;
    elsif (rising_edge(clk) and state /= st0) then
    case state is
    when st0 =>
    when st1 =>
    state <= st2;
    when st2 =>
    state <= st3;
    when st3 =>
    state <= st0;
    end case;
    end if;
    end process;
    end Behavioral;


    end the error is:
    ERROR:Xst:827 - main.vhd line 23: Signal state cannot be synthesized,
    bad synchronous description.

    How can I implement my state machine?

    thanks
    Max, Sep 10, 2003
    #1
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  2. On 10 Sep 2003 03:50:49 -0700, (Max) wrote:

    >I need that my state machine starts on rising_edge of a signal, then
    >it must be synchronous with clk. When the last state has been
    >executed, I must wait a rising_edge again:
    >
    >I wrote this:
    >
    >architecture Behavioral of main is
    >type state_type is (ST0, ST1, ST2, ST3);
    >signal state: state_type;
    >
    >begin
    >
    >process (clk, start, reset)
    >begin
    > if reset = '1' then
    > state <= st0;
    > elsif (rising_edge(start) and state = st0) then
    > state <= st1;
    > elsif (rising_edge(clk) and state /= st0) then
    > case state is
    > when st0 =>
    > when st1 =>
    > state <= st2;
    > when st2 =>
    > state <= st3;
    > when st3 =>
    > state <= st0;
    > end case;
    > end if;
    >end process;
    >end Behavioral;
    >
    >end the error is:
    >ERROR:Xst:827 - main.vhd line 23: Signal state cannot be synthesized,
    >bad synchronous description.
    >
    >How can I implement my state machine?


    The basic problem is that you are using two clocks (start and clk) on
    the same flip flops. This probably isn't what you wanted, and will
    cause the synthesiser to barf.

    I suggest you rethink your design. You also might like to google for
    "vhdl clocked process template".

    Does it really need to be sensitive to the rising edge of start? The
    problem is much simpler if you can sample start with a flip flop (i.e.
    it goes into the D input, not the Clk input).

    If you really need to trigger on the edge of start (perhaps because it
    has a pulse width that's smaller than the period of clk) then this
    should be done with a separate flip flop that produces a longer signal
    that your state machine can sample.

    Regards,
    Allan.
    Allan Herriman, Sep 10, 2003
    #2
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  3. Your synthesizer should understand this. This assumes that
    start is synchronous to clk:

    process (clk, reset)
    begin
    if reset = '1' then
    state <= st0;
    elsif (clk'event and clk='1' ) then
    case state is
    when st0 =>
    if(start ='1') then
    state <= st1;
    end if;
    when st1 =>
    state <= st2;
    when st2 =>
    state <= st3;
    when st3 =>
    state <= st0;
    end case;
    end if;
    end process;

    (Max) wrote in message news:<>...
    > I need that my state machine starts on rising_edge of a signal, then
    > it must be synchronous with clk. When the last state has been
    > executed, I must wait a rising_edge again:
    >
    > I wrote this:
    >
    > architecture Behavioral of main is
    > type state_type is (ST0, ST1, ST2, ST3);
    > signal state: state_type;
    >
    > begin
    >
    > process (clk, start, reset)
    > begin
    > if reset = '1' then
    > state <= st0;
    > elsif (rising_edge(start) and state = st0) then
    > state <= st1;
    > elsif (rising_edge(clk) and state /= st0) then
    > case state is
    > when st0 =>
    > when st1 =>
    > state <= st2;
    > when st2 =>
    > state <= st3;
    > when st3 =>
    > state <= st0;
    > end case;
    > end if;
    > end process;
    > end Behavioral;
    >
    >
    > end the error is:
    > ERROR:Xst:827 - main.vhd line 23: Signal state cannot be synthesized,
    > bad synchronous description.
    >
    > How can I implement my state machine?
    >
    > thanks
    William Wallace, Sep 10, 2003
    #3
  4. Hi Max!


    > I need that my state machine starts on rising_edge of a signal, then
    > it must be synchronous with clk. When the last state has been
    > executed, I must wait a rising_edge again:
    >
    > I wrote this:
    >
    > architecture Behavioral of main is
    > type state_type is (ST0, ST1, ST2, ST3);
    > signal state: state_type;
    >
    > begin
    >
    > process (clk, start, reset)
    > begin
    > if reset = '1' then
    > state <= st0;
    > elsif (rising_edge(start) and state = st0) then
    > state <= st1;
    > elsif (rising_edge(clk) and state /= st0) then
    > case state is
    > when st0 =>
    > when st1 =>
    > state <= st2;
    > when st2 =>
    > state <= st3;
    > when st3 =>
    > state <= st0;
    > end case;
    > end if;
    > end process;
    > end Behavioral;
    >
    >
    > end the error is:
    > ERROR:Xst:827 - main.vhd line 23: Signal state cannot be synthesized,
    > bad synchronous description.


    Dual-edge flipflops are not supported (up to today) by synthesis.


    Because your specifications cover ot all cases, I can only write a
    "template", that has to be improved to fit your real specifications:

    process(start, reset, state)
    begin
    if reset = '1' then
    go <= '0';
    elsif rising_edge(start) then
    if (state=st1) then
    go <= '1';
    end if;
    end if;
    end process;

    process(reset,clk)
    if (reset='1') then
    state <= st1;
    elsif rising_edge(clk) then
    if (go = '1') then
    case state is
    -- write your state logic
    end case;
    end if;
    end if;
    end process;


    Seems to me, that this was the same question like some days ago. Why did
    you not follow my hints with the 3 counters? Did the spcification change?

    Ralf
    Ralf Hildebrandt, Sep 10, 2003
    #4
  5. Then add a st4_wait_low like st0, and modify st3. If start can be any
    length (integral number of clocks) high and low, then you'll have to
    take that into account, too, for st1, st2, and st3 accordingly.

    when st3 =>
    if (start ='0') then
    state <= st0;
    else
    state <= st4_wait_low ;
    end if;
    when st4_wait_low =>
    if (start ='0') then
    state <= st0; -- now go wait for rising edge
    end if;


    > Your synthesizer should understand this. This assumes that
    > start is synchronous to clk:
    >
    > process (clk, reset)
    > begin
    > if reset = '1' then
    > state <= st0;
    > elsif (clk'event and clk='1' ) then
    > case state is
    > when st0 =>
    > if(start ='1') then
    > state <= st1;
    > end if;
    > when st1 =>
    > state <= st2;
    > when st2 =>
    > state <= st3;
    > when st3 =>
    > state <= st0;
    > end case;
    > end if;
    > end process;

    this work only if start goes low before st3. If start remains '1'
    after
    st3, the machine goes in st0 and immediatly restart instead of wait
    the
    next rising_edge(start).



    (Max) wrote in message
    news:<>...
    > I need that my state machine starts on rising_edge of a signal, then
    > it must be synchronous with clk. When the last state has been
    > executed, I must wait a rising_edge again:
    >
    > I wrote this:
    >
    > architecture Behavioral of main is
    > type state_type is (ST0, ST1, ST2, ST3);
    > signal state: state_type;
    >
    > begin
    >
    > process (clk, start, reset)
    > begin
    > if reset = '1' then
    > state <= st0;
    > elsif (rising_edge(start) and state = st0) then
    > state <= st1;
    > elsif (rising_edge(clk) and state /= st0) then
    > case state is
    > when st0 =>
    > when st1 =>
    > state <= st2;
    > when st2 =>
    > state <= st3;
    > when st3 =>
    > state <= st0;
    > end case;
    > end if;
    > end process;
    > end Behavioral;
    >
    >
    > end the error is:
    > ERROR:Xst:827 - main.vhd line 23: Signal state cannot be synthesized,
    > bad synchronous description.
    >
    > How can I implement my state machine?
    >
    > thanks
    William Wallace, Sep 10, 2003
    #5
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