aggregate assignments

Discussion in 'VHDL' started by ed.agunos@gmail.com, Jan 9, 2009.

  1. Guest

    we can do stuff like this:

    signal some_signal : std_logic_vector(15 downto 0);

    some_signal <= (15 downto 12 => '1', others => '0');

    BUT.... is there someway we can do something like this:

    some_signal <= (15 downto 12 => "1010", others => '0');

    Thanks in advance :)
     
    , Jan 9, 2009
    #1
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  2. Dave Guest

    On Jan 9, 6:57 pm, wrote:
    > we can do stuff like this:
    >
    >     signal some_signal : std_logic_vector(15 downto 0);
    >
    >     some_signal <= (15 downto 12 => '1', others => '0');
    >
    > BUT.... is there someway we can do something like this:
    >
    >     some_signal <= (15 downto 12 => "1010", others => '0');
    >
    > Thanks in advance :)


    How about:

    some_signal <= (others => '0');
    some_signal(15 downto 12) <= "1010";

    Dave
     
    Dave, Jan 10, 2009
    #2
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  3. uhu01

    Joined:
    Jan 10, 2009
    Messages:
    1
    Hi,

    I'm not a VHDL Pro, but the first thing that comes to my mind is something like:

    constant zeroes : std_logic_vector(11 downto 0) := "00000000000";
    some_signal <= "1010" & zeroes;

    Regards,
    Andreas
     
    uhu01, Jan 10, 2009
    #3
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