AHB protocol document - clarification

[anupam.jain21]

Hello

The AHB protocol document ARM IHI 0011A has the following statement(sec
3.8)

The minimum address space that can be allocated to a single slave is
1kB. All the bus masters are designed such that they will not perform
incrementing transfers over a 1kB boudary,thus ensuring that a burst
never crosses an addess decode boundary.

I see no relation between the first two sentences.Is there any? or
they are simply two independent conditions.
The second sentence also is not clear to me ,can anyone give a brief
explanation for the same.


regards,
Anupam Jain

 

[Stephane]

Hello

The AHB protocol document ARM IHI 0011A has the following statement(sec
3.8)

The minimum address space that can be allocated to a single slave is
1kB. All the bus masters are designed such that they will not perform
incrementing transfers over a 1kB boudary,thus ensuring that a burst
never crosses an addess decode boundary.

I see no relation between the first two sentences.Is there any? or
they are simply two independent conditions.

yes, they seem rather independent

The second sentence also is not clear to me ,can anyone give a brief
explanation for the same.

I understand the address incrementer of the master would roll to zero
when reaching the 1k boundary; so to avoid what could be ambiguous, the
protocol forbids such boundary crossing.

 

[Charles, NG]

The two issues are related.

1) The minimum address space that can be allocated to a single slave is 1kB.

This refers to the memory granularity when designing your memory map. If
your mini-system has two slaves and each has just one register, then the
two registers must reside in separate memory pages
(e.g. REG1 = 0x0004 # In Page 0,
REG2 = 0x0400 # In Page 1)

-------------

2)All the bus masters are designed such that they will not perform
incrementing transfers over a 1kB boudary,thus ensuring that a burst
never crosses an addess decode boundary.

I seem to remember this being explained elsewhere in the spec as well,
but basically it has to do with how a slave recognises whether it is the
target of a request or not. A slave recognises selection when HTRANS =
NSEQ and its HSEL is active. For the rest of a burst transfer (HTRANS =
SEQ), a slave can continue to consider itself selected until it sees
either a new address cycle with HTRANS = NSEQ or HTRANS = IDLE. If a
master bursted across a 1K boundary (i.e. into the next page) the first
slave might or might not remain selected and the second slave might or
might-not pick up selection (it really shouldn't though even if it's
HSEL = 1 when HTRANS != NSEQ)

So really the two statements are the two different views to the AMBA AHB
rules for memory-space granularity. The first statement is from the
slave point of view and the second statement is from the master point of
view.

Hope this helps

Regards,
Charles

 

[anupam.jain21]

I seem to remember this being explained elsewhere in the spec as well,
but basically it has to do with how a slave recognises whether it is the
target of a request or not. A slave recognises selection when HTRANS =
NSEQ and its HSEL is active. For the rest of a burst transfer (HTRANS =
SEQ), a slave can continue to consider itself selected until it sees
either a new address cycle with HTRANS = NSEQ or HTRANS = IDLE. If a
master bursted across a 1K boundary (i.e. into the next page) the first
slave might or might not remain selected and the second slave might or
might-not pick up selection (it really shouldn't though even if it's
HSEL = 1 when HTRANS != NSEQ)

So really the two statements are the two different views to the AMBA AHB
rules for memory-space granularity. The first statement is from the
slave point of view and the second statement is from the master point of
view.

hi,
A new page doesn't mean a new slave .Because the first statement says
that the minimum address space of a slave should be 1k and so no limit
on maximum space.
So if the 1k boundary is crossed ,it shouldn't matter as there is HSEL
signal to select a slave which is a combinatorial decode of higher
order address bus.
Could n't get what you were trying to explain....

regards,
Anupam Jain