AHDL program: HELP!

Discussion in 'VHDL' started by msigwald@gmail.com, Nov 5, 2006.

  1. Guest

    I know this is a VHDL group, however, since there is no AHDL group and
    I read more than one post in which people talked about using or having
    used AHDL I suppose I can find some help in here.
    This is the code:

    SUBDESIGN FlipD
    (
    D,LE,CL,PS :INPUT;
    Q :OUTPUT;
    )

    VARIABLE
    tmp[1..0] :NODE; %store latches outputs%
    en,out :NODE; %Enable of slave latch and master-latch output%
    %prep[1..0] :NODE; %Array of preparatory states%

    BEGIN

    tmp[0]=out; %copies MASTER-output%
    tmp[1]=Q; %copies SLAVE-output%
    en=!LE; %SLAVE latch-enable (negation of LE)%
    prep[]=(PS,CL);

    IF(LE==VCC) THEN %Latch-Enable on%

    CASE prep[] IS
    WHEN b"01"=>% CL activated, out goes to GND%
    out=GND;
    WHEN b"10"=>%PS activated, out goes to VCC%
    out=VCC;
    WHEN OTHERS=>%any other combination: transparent latch%
    out=D;

    END CASE;
    END IF;
    ELSE
    out=tmp[0]; %MASTER-output remains the same%
    END IF;

    IF(en==VCC) THEN %if slave is enabled%
    Q=out; %update output value by copying MASTER output%
    ELSE
    Q=tmp[1];%SLAVE output remains the same%
    END IF;
    END;

    What I'm trying to do with this code is a D type Flip-Flop. The funny
    thing is that if I remove the CASE block (which analices CL and PS
    inputs), the thing works just right, but when I try to simulate the
    whole program (with CL and PS set in any different values, it doesn't
    make a difference) the output gets stucked at VCC forever.
    Any ideas?
    , Nov 5, 2006
    #1
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