[AHDL]

Discussion in 'VHDL' started by news1.ustronie.pw.edu.pl, Apr 29, 2006.

  1. Hi!

    I couldn't find group for AHDL so I decided to write here.
    I have proble with writing value to register.
    my register:
    register[7..0] : DFF;
    my constatnt
    CONSTANT TIME = H"23";

    and when I am tring like this

    register[] = TIME;

    I see in my simulator register's value :
    XX1XXX11

    Is anybody can tell my wy there are 'X' instead '0' ?

    Thanks in advance

    --
    grzesiek
    news1.ustronie.pw.edu.pl, Apr 29, 2006
    #1
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  2. news1.ustronie.pw.edu.pl

    Andy Guest

    AHDL is a proprietary language owned by Altera.

    Strangely, Xilinx webpack has an AHDL -> VHDL translator, but Altera
    does not...

    If possible, I would suggest abandoning AHDL, in favor of vhdl.

    Andy
    Andy, May 1, 2006
    #2
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  3. news1.ustronie.pw.edu.pl

    Hilko Guest

    Hi,

    i think Altera optimizes away the bits that stuck to gnd.
    Try to lay register[] on an output......


    CONSTANT TIME = H"23";
    subdesign test
    (
    clk : input;
    register[7..0] : output;
    )

    variable
    register[7..0] : DFF;

    begin
    register[].clk = clk;
    register[] = TIME;
    end;

    Then it should work. I know it's ugly but i don't see another
    way to prevent Altera from optimizing.

    Hilko
    Hilko, May 2, 2006
    #3
  4. news1.ustronie.pw.edu.pl

    Andy Peters Guest

    Andy wrote:
    > AHDL is a proprietary language owned by Altera.
    >
    > Strangely, Xilinx webpack has an AHDL -> VHDL translator, but Altera
    > does not...


    That's really an Altera-to-Xilinx conversion feature.

    -a
    Andy Peters, May 2, 2006
    #4
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