Altera Quartus, libraries and mixed VHDL / (SYSTEM)VERILOG error

[Peter Bluer]

I'm trying to run a design through Quartus II which is a mixture of VHDL,
Verilog and system verilog.

I can compile it for modelsim outside of quartus and it simulates fine,
however I get errors when running through the quartus mapper.

In quartus I add files into a library called 'design', an example of this
is:

set_global_assignment -name SYSTEMVERILOG_FILE -library design
$SV_PATH/counter.sv

These files are found by quartus:

Info: Found 1 design units, including 1 entities, in source file counter.sv
Info: Found entity 1: counter

If I check the file list the files are specified to be in the library
'design'.

However, when I run the mapper I get this error:

Error (10481): VHDL Use Clause error at mydesign.vhd(446): design library
"design" does not contain primary unit "counter" File: mydesign.vhd Line:
446

The VHDL file mydesign.vhd snippet with this block in is:

LIBRARY design:
CONFIGURATION DUMMY of top IS
FOR struct
For counter_c : counter
USE ENTITY design.counter(counter); <---- Line 446
END FOR;
..
..
..
END CONFIGURATION DUMMY;

Can anyone tell from this what may be causing the error?

Thank you.

 

[Mike Treseler]

Error (10481): VHDL Use Clause error at mydesign.vhd(446): design
library "design" does not contain primary unit "counter" File:
mydesign.vhd Line: 446

The VHDL file mydesign.vhd snippet with this block in is:

LIBRARY design:

^
This is a syntax error. There is no library declaration in vhdl.

CONFIGURATION DUMMY of top IS
FOR struct
For counter_c : counter
USE ENTITY design.counter(counter); <---- Line 446

USE ENTITY work.counter(counter); -- try this instead.

-- Mike Treseler