Ambigous operator '&'

Discussion in 'VHDL' started by Mohammed A khader, Apr 20, 2005.

  1. HI all,

    While compiling my design in Quartus II 4.2 , I got following errors.
    The piece of code is given below....

    Error: VHDL error at Ctrl_Ram.Vhd(66): can't determine definition of
    operator ""&"" -- found 2 possible definitions
    Error: Verilog HDL or VHDL error at Ctrl_Ram.Vhd(66): Unconverted
    VHDL-1402: ambiguous type: 'Regfile' or 'SIGNED'
    Error: VHDL Type Conversion error at Ctrl_Ram.Vhd(66): can't determine
    type of object or expression near text or symbol "UNSIGNED"
    Error: Ignored construct Ctrl_Ram_Arch at Ctrl_Ram.Vhd(42) because of
    previous errors


    -- These subtypes are in a package....

    subtype WORD is signed(15 downto 0);
    subtype DWORD is unsigned(31 downto 0);


    -- In the Architecture declaration part I am defining follwing
    signals..


    type Regfile is array (natural range<>) of WORD;
    signal Regfile_Ctrl_High : Regfile(0 to 15); -- High Bank Registe File
    signal Regfile_Ctrl_Low : Regfile(0 to 15); -- Low Bank Register File

    signal data_out_high : WORD;
    signal data_out_low : WORD;


    -- And these are the concurrent statements in Architecture body...

    -- Regfile Read Assignments
    data_out_low <= Regfile_Ctrl_Low(TO_INTEGER(Addrs_In));
    data_out_high <= Regfile_Ctrl_High(TO_INTEGER(Addrs_In));

    -- Concatenation of Low and High to form 32 Control Word
    Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
    THIS LINE...

    Whats wrong with the last statment. I expect '&' operator to
    concatenate the two signals. What could be the other meaning of '&'
    operator. I think I am doing a silly mistake some where . Please help
    me in resolving this..

    Thanks.
    -- Mohammed A Khader.
    Mohammed A khader, Apr 20, 2005
    #1
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  2. >
    > -- Concatenation of Low and High to form 32 Control Word
    > Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
    > THIS LINE...
    >


    >


    -- just try
    Data32_Out <= unsigned(data_out_high) & unsigned(data_out_low);

    regards,
    laurent gauch
    www.amontec.com
    Laurent Gauch, Apr 20, 2005
    #2
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  3. Thanks ! It Worked .. But both are logically equal. What was my
    mistake ?
    Mohammed A khader, Apr 20, 2005
    #3
  4. On 20 Apr 2005 03:48:55 -0700, Mohammed A khader wrote:

    > -- Concatenation of Low and High to form 32 Control Word
    > Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
    > THIS LINE...
    >
    > Whats wrong with the last statment. I expect '&' operator to
    > concatenate the two signals. What could be the other meaning of '&'
    > operator. I think I am doing a silly mistake some where . Please help
    > me in resolving this..


    With '&' you can (1) concatenate two arrays. For example, when using two
    arrays of std_login (aka std_logic_vector):
    "000" & "111"
    This will create a 6 element long array.
    With '&' you can (2) append or (3) prepend a single element to an array:
    "000" & '1'
    '0' & "111"
    This will create a 4 element long array. Note that it is syntactically
    different from "0" & "111", which I described in (1).
    With '&' you can (4) create a new array by concatenating two elements:
    '0' & '1'
    This will create a 2 element array.


    Now, this works not only with std_logic_vector, but with any array. For
    example, with this one:

    > type Regfile is array (natural range<>) of WORD;


    Now we have two different interpretations of
    data_out_high & data_out_low
    It can either produce a signed(0 to 31) (VHDL-93) according to (1), or a
    Regfile(0 to 1) according to (4).


    Laurent showed one way to avoid this problem. My first guess would have
    been something like
    Data32_Out <= unsigned(signed(data_out_high) & signed(data_out_low));
    which is closer to your original code. Maybe the following would work:
    Data32_Out <= unsigned(signed'(data_out_high & data_out_low));
    But I'm not sure. (Please note the tick.)


    [xp and f'up2 comp.lang.vhdl]

    Sebastian
    Sebastian Weiser, Apr 20, 2005
    #4
  5. Mohammed A khader wrote:
    > But both are logically equal.
    > What was my mistake ?


    Using & on your own array types
    without writing an overload for "&".
    Probably easier to use the predefined &
    for unsigned as Laurent suggests.

    If these are process statements, you could also say:

    Data32_Out(31 downto 16) <= unsigned(data_out_high);
    Data32_Out(15 downto 0) <= unsigned(data_out_low);

    -- Mike Treseler
    Mike Treseler, Apr 20, 2005
    #5
  6. HI Mike,

    > Using & on your own array types without writing an overload for "&".


    my signals 'data_out_high' and 'data_out_low' are subtype of signed.
    Hence I expect that sysnthesis tool does'nt consider it as a new type.
    Mohammed A khader, Apr 22, 2005
    #6
  7. Mohammed A khader wrote:

    > my signals 'data_out_high' and 'data_out_low' are subtype of signed.
    > Hence I expect that sysnthesis tool does'nt consider it as a new type.


    When you declare an array type like Regfile,
    you automatically get new "&" functions
    to combine arrays and to add
    an element to the array.
    In this case, an element of Regfile
    is indistinguishable from a WORD.

    Data32_Out <= unsigned(data_out_high) & unsigned(data_out_low);

    Works in all cases
    because & for unsigned
    is the only possibility

    Data32_Out <= unsigned'(data_out_high & data_out_low);

    Works only if you change the
    WORD declaration to
    unsigned(31 downto 0)
    otherwise:
    Ambiguous type: 'regfile' or 'signed'.


    Data32_Out <= unsigned(data_out_high & data_out_low);

    Ambiguous type: 'regfile' or 'signed'.
    No easy way to make this do what
    you expect without removing the
    Regfile type declaration.

    -- Mike Treseler
    Mike Treseler, Apr 22, 2005
    #7
  8. On Wed, 20 Apr 2005 11:14:59 -0700, Mike Treseler wrote:

    > Using & on your own array types
    > without writing an overload for "&".


    Hmm, that differs from my explanation.

    I've never seen an explicit overloading of the "&" operator, since it is
    AFAIK implicitly given for any array type.


    Sebastian
    Sebastian Weiser, Apr 24, 2005
    #8
  9. Sebastian Weiser wrote:

    > I've never seen an explicit overloading of the "&" operator, since it is
    > AFAIK implicitly given for any array type.


    I agree.
    The OP's problem was
    too many overloads,
    not too few.

    -- Mike Treseler
    Mike Treseler, Apr 24, 2005
    #9
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