and bitwise operation on std_logic_vector bits

[Hannes]

Hello,

I am relatively new to VHDL.

I search for a command to realize a Boolean OR operation on all bits of
a std_logic_vector in a compact way.

example:

signal a : std_logic vector (3 downto 0);
signal b : std_logic;

b <= a(0) or a(1) or a(2) or a(3);



this solution works fine with four bits, but with larger vectors it is
not very comfortable.
Do somebody have an idea?

Regards

Hannes

 

[HT-Lab]

VHDL2008 supports reduction operators,

b<= OR a;

Hans
www.ht-lab.com


"Hannes" wrote in message

Hello,

I am relatively new to VHDL.

I search for a command to realize a Boolean OR operation on all bits of
a std_logic_vector in a compact way.

example:

signal a : std_logic vector (3 downto 0);
signal b : std_logic;

b <= a(0) or a(1) or a(2) or a(3);



this solution works fine with four bits, but with larger vectors it is
not very comfortable.
Do somebody have an idea?

Regards

Hannes

 

[Hannes]

Thank you,

regards

Hannes

 

[backhus]

Thank you,

regards

Hannes

Hi,
nice tip for the future, when all tools finally support VHDL 2008.
For now, you can find reduce-functions in std_logic_misc.
e.g.
function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;

function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;

Have a nice synthesis
Eilert

 

[Thomas Stanka]

signal a : std_logic vector (3 downto 0);
signal b : std_logic;

b <= a(0) or a(1) or a(2) or a(3);

beside the defined reduce functions(see other post in this thread) you
could use a for-loop as generic solution to do bitwise reduction for
any function.

for i in a'range loop
b_var := b_var or a(i);
c_var := my_function(c_var, a(i));
end loop

bye Thomas

 

[Andy]

beside the defined reduce functions(see other post in this thread) you
could use a for-loop as generic solution to do bitwise reduction for
any function.

for i in a'range loop
  b_var := b_var or a(i);
  c_var := my_function(c_var, a(i));
end loop

bye Thomas

Don't forget to initialize b_var before entering the loop!

Depending on the arbitrary function, the initialization value may
differ. Hint: initialize it to first bit of a() and skip that bit in
the loop.

Andy

 

[Paul Uiterlinden]

Hello,

I am relatively new to VHDL.

I search for a command to realize a Boolean OR operation on all bits of
a std_logic_vector in a compact way.

example:

signal a : std_logic vector (3 downto 0);
signal b : std_logic;

b <= a(0) or a(1) or a(2) or a(3);

b <= '0' WHEN a = (a'range => '0') ELSE '1';

Caveat: it does not handle weak values such as 'L' and 'H'. If that is a
concern, you can use:

b <= '0' WHEN to_x01(a) = (a'range => '0') ELSE '1';

Function to_x01 is defined in ieee.std_logic_1164.