and bitwise operation on std_logic_vector bits

Discussion in 'VHDL' started by Hannes, Feb 14, 2011.

  1. Hannes

    Hannes Guest

    Hello,

    I am relatively new to VHDL.

    I search for a command to realize a Boolean OR operation on all bits of
    a std_logic_vector in a compact way.

    example:

    signal a : std_logic vector (3 downto 0);
    signal b : std_logic;

    b <= a(0) or a(1) or a(2) or a(3);



    this solution works fine with four bits, but with larger vectors it is
    not very comfortable.
    Do somebody have an idea?

    Regards

    Hannes
     
    Hannes, Feb 14, 2011
    #1
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  2. Hannes

    HT-Lab Guest

    VHDL2008 supports reduction operators,

    b<= OR a;

    Hans
    www.ht-lab.com


    "Hannes" wrote in message news:...

    Hello,

    I am relatively new to VHDL.

    I search for a command to realize a Boolean OR operation on all bits of
    a std_logic_vector in a compact way.

    example:

    signal a : std_logic vector (3 downto 0);
    signal b : std_logic;

    b <= a(0) or a(1) or a(2) or a(3);



    this solution works fine with four bits, but with larger vectors it is
    not very comfortable.
    Do somebody have an idea?

    Regards

    Hannes
     
    HT-Lab, Feb 14, 2011
    #2
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  3. Hannes

    Hannes Guest

    Thank you,

    regards

    Hannes

    On 02/14/2011 05:43 PM, HT-Lab wrote:
    > VHDL2008 supports reduction operators,
    >
    > b<= OR a;
    >
    > Hans
    > www.ht-lab.com
    >
    >
    > "Hannes" wrote in message news:...
    > Hello,
    >
    > I am relatively new to VHDL.
    >
    > I search for a command to realize a Boolean OR operation on all bits of
    > a std_logic_vector in a compact way.
    >
    > example:
    >
    > signal a : std_logic vector (3 downto 0);
    > signal b : std_logic;
    >
    > b <= a(0) or a(1) or a(2) or a(3);
    >
    >
    >
    > this solution works fine with four bits, but with larger vectors it is
    > not very comfortable.
    > Do somebody have an idea?
    >
    > Regards
    >
    > Hannes
    >
     
    Hannes, Feb 14, 2011
    #3
  4. Hannes

    backhus Guest

    On 14 Feb., 18:51, Hannes <"h.mcchoc"@gmx.de> wrote:
    > Thank you,
    >
    > regards
    >
    > Hannes
    >
    > On 02/14/2011 05:43 PM, HT-Lab wrote:
    >
    > > VHDL2008 supports reduction operators,

    >
    > > b<= OR a;

    >
    > > Hans
    > >www.ht-lab.com

    >
    > > "Hannes"  wrote in messagenews:...
    > > Hello,

    >
    > > I am relatively new to VHDL.

    >
    > > I search for a command to realize a Boolean OR operation on all bits of
    > > a std_logic_vector in a compact way.

    >
    > > example:

    >
    > > signal a : std_logic vector (3 downto 0);
    > > signal b : std_logic;

    >
    > > b <= a(0) or a(1) or a(2) or a(3);

    >
    > > this solution works fine with four bits, but with larger vectors it is
    > > not very comfortable.
    > > Do somebody have an idea?

    >
    > > Regards

    >
    > > Hannes

    >
    >


    Hi,
    nice tip for the future, when all tools finally support VHDL 2008.
    For now, you can find reduce-functions in std_logic_misc.
    e.g.
    function AND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
    function NAND_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
    function OR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
    function NOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
    function XOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;
    function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR) return UX01;

    function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
    function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
    function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
    function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
    function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
    function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;

    Have a nice synthesis
    Eilert
     
    backhus, Feb 15, 2011
    #4
  5. On 14 Feb., 16:50, Hannes <"h.mcchoc"@gmx.de> wrote:

    > signal a : std_logic vector (3 downto 0);
    > signal b : std_logic;
    >
    > b <= a(0) or a(1) or a(2) or a(3);


    beside the defined reduce functions(see other post in this thread) you
    could use a for-loop as generic solution to do bitwise reduction for
    any function.

    for i in a'range loop
    b_var := b_var or a(i);
    c_var := my_function(c_var, a(i));
    end loop

    bye Thomas
     
    Thomas Stanka, Feb 15, 2011
    #5
  6. Hannes

    Andy Guest

    On Feb 15, 8:59 am, Thomas Stanka <>
    wrote:
    > On 14 Feb., 16:50, Hannes <"h.mcchoc"@gmx.de> wrote:
    >
    > > signal a : std_logic vector (3 downto 0);
    > > signal b : std_logic;

    >
    > > b <= a(0) or a(1) or a(2) or a(3);

    >
    > beside the defined reduce functions(see other post in this thread) you
    > could use a for-loop as generic solution to do bitwise reduction for
    > any function.
    >
    > for i in a'range loop
    >   b_var := b_var or a(i);
    >   c_var := my_function(c_var, a(i));
    > end loop
    >
    > bye Thomas


    Don't forget to initialize b_var before entering the loop!

    Depending on the arbitrary function, the initialization value may
    differ. Hint: initialize it to first bit of a() and skip that bit in
    the loop.

    Andy
     
    Andy, Feb 15, 2011
    #6
  7. Hannes wrote:

    > Hello,
    >
    > I am relatively new to VHDL.
    >
    > I search for a command to realize a Boolean OR operation on all bits of
    > a std_logic_vector in a compact way.
    >
    > example:
    >
    > signal a : std_logic vector (3 downto 0);
    > signal b : std_logic;
    >
    > b <= a(0) or a(1) or a(2) or a(3);


    b <= '0' WHEN a = (a'range => '0') ELSE '1';

    Caveat: it does not handle weak values such as 'L' and 'H'. If that is a
    concern, you can use:

    b <= '0' WHEN to_x01(a) = (a'range => '0') ELSE '1';

    Function to_x01 is defined in ieee.std_logic_1164.

    --
    Paul Uiterlinden
    www.aimvalley.nl
    e-mail addres: remove the not.
     
    Paul Uiterlinden, Feb 16, 2011
    #7
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