AND or OR function across a vector

Discussion in 'VHDL' started by Hitchkas, Sep 16, 2005.

  1. Hitchkas

    Hitchkas Guest

    I want to implement an OR function across a STD_LOGIC_VECTOR. For
    exampe the equivalent of;

    signal bus : std_logic_vector(3 downto 0);
    signal result : std_logic;

    result <= bus(3) or bus(2) or bus(1) or bus(0);

    rather than typing all the input signals one by one, is there a
    shorthand notation, or is there a standard package to do so?

    for example something like "result <= Or(bus);"

    I have done something like the following but I am not sure if this is
    the best way to do it. I need to do this since the bus width is a
    generic parameter and not known before hand.

    process (bus)
    begin
    result <= '0';
    for I in bus'Range loop
    if bus(I) = '1' Or bus(I) = 'H' then
    result <= '1';
    exit;
    elsif bus(I) = 'X' then
    result <= 'X';
    else
    null;
    end if;
    end loop;
    end process;


    Thanks in advance
    Hitchkas, Sep 16, 2005
    #1
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  2. Hitchkas

    SKeffect Guest

    I guess you can very simply do it like this


    result <= '1' when bus /= ALL_ZEROS else '0' ;

    put this declaration in the signal declaration section

    CONSTANT ALL_ZEROS : std_logic_vector(GENERIC_WIDTH-1 downto 0) :=
    (others => '0') ;

    Cheers,
    SK

    Hitchkas wrote:
    > I want to implement an OR function across a STD_LOGIC_VECTOR. For
    > exampe the equivalent of;
    >
    > signal bus : std_logic_vector(3 downto 0);
    > signal result : std_logic;
    >
    > result <= bus(3) or bus(2) or bus(1) or bus(0);
    >
    > rather than typing all the input signals one by one, is there a
    > shorthand notation, or is there a standard package to do so?
    >
    > for example something like "result <= Or(bus);"
    >
    > I have done something like the following but I am not sure if this is
    > the best way to do it. I need to do this since the bus width is a
    > generic parameter and not known before hand.
    >
    > process (bus)
    > begin
    > result <= '0';
    > for I in bus'Range loop
    > if bus(I) = '1' Or bus(I) = 'H' then
    > result <= '1';
    > exit;
    > elsif bus(I) = 'X' then
    > result <= 'X';
    > else
    > null;
    > end if;
    > end loop;
    > end process;
    >
    >
    > Thanks in advance
    >
    SKeffect, Sep 16, 2005
    #2
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  3. Hitchkas

    Peter Guest

    Or:

    result <= '0' when bus = (bus'range => '0') else '1';

    /Peter
    Peter, Sep 16, 2005
    #3
  4. Hitchkas

    Andy Peters Guest

    Hitchkas wrote:
    > I want to implement an OR function across a STD_LOGIC_VECTOR. For
    > exampe the equivalent of;
    >
    > signal bus : std_logic_vector(3 downto 0);
    > signal result : std_logic;
    >
    > result <= bus(3) or bus(2) or bus(1) or bus(0);
    >
    > rather than typing all the input signals one by one, is there a
    > shorthand notation, or is there a standard package to do so?
    >
    > for example something like "result <= Or(bus);"


    Ah, the reduction-OR operator. One of the few areas where Verilog does
    something VHDL doesn't.

    google for "reduction-OR VHDL" -- there's a few examples.

    -a
    Andy Peters, Sep 16, 2005
    #4
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