/ and rem, is it synthesizable if the first operand is a power of 2?

[sonny]

Hi

A question to ask about synthesizable codes.
i have read some posts here about division issues.

in my code i should use two integer values, which are signals and
variables. and they need to be divided by 2, 4, 6, 8 and so on. i
heard that / and rem are synthesizable if the first operand is a power
of 2?

for example,
integer / integer (1st operand)
integer rem integer (1st operand)

any kinda posts will be helpful....thx

sonny

 

[KJ]

Hi

A question to ask about synthesizable codes.
i have read some posts here about division issues.

in my code i should use two integer values, which are signals and
variables. and they need to be divided by 2, 4, 6, 8 and so on. i
heard that / and rem are synthesizable if the first operand is a power
of 2?

for example,
integer / integer (1st operand)
integer rem integer (1st operand)

any kinda posts will be helpful....thx

sonny

1. / and rem are synthesizable regardless of whether the values are
certain values or not.
2. Whether or not your particular tool supports / and rem for
arbitrary input signals is a tool dependent question...consult your
manual for coding guidelines
3. Usually the tool restriction is on the second operand (i.e. the
denominator) not the first and the restriction is that it be both a
constant (i.e. not a signal) and be a power of 2, which are
2,4,8,16...not 2,4,6,8 as you listed. The reason for this is that
division by a constant that happens to be is a power of 2 can be
implemented with a simple shift.
4. If you really need to divide two signals and not be restricted,
check into using the lpm_divide component.

KJ

 

[Andy]

1. / and rem are synthesizable regardless of whether the values are
certain values or not.
2. Whether or not your particular tool supports / and rem for
arbitrary input signals is a tool dependent question...consult your
manual for coding guidelines
3. Usually the tool restriction is on the second operand (i.e. the
denominator) not the first and the restriction is that it be both a
constant (i.e. not a signal) and be a power of 2, which are
2,4,8,16...not 2,4,6,8 as you listed. The reason for this is that
division by a constant that happens to be is a power of 2 can be
implemented with a simple shift.
4. If you really need to divide two signals and not be restricted,
check into using the lpm_divide component.

KJ

Generally, synthesis of /, rem and mod are limited to cases where the
2nd operand (right hand operand) is a "static" power of 2, or where
both operands are "static". Note that for synthesis, my use of
"static" encompases more than the VHDL language definition of
"static". For instance, for-loop indices are considered "static" for
synthesis, since the loop is unrolled anyway. In short, almost any
expression that can be computed at analysis/elaboration (compile) time
is "static" for synthesis, since no hardware has to be created
anyway.

Also note that this expanded definition for "static" during synthesis
is not transferable to language requirements for globally static and
locally static expressions (i.e. case statement targets, etc.), which
must still meet the more stringent LRM definition.

Andy