V
Vikram
There are two distinct phases in bringing an FPGA system to market:
the design phase and the debug and
verification phase. The primary tasks in the design phase are entry,
simulation, and implementation. The primary tasks in the Debug and
Verification phase are to validate the design and correct any bugs
found.
The recent advancements in FPGA densities have changed the way we
think of design & debug of a FPGA. This camp will focus on what can
you do as an engineer to make debugging your FPGA a science rather
then an art. It will also introduce to you various tools that you can
use to shorten the debug cycle.
Agenda: Tentative
5:00 PM- 6:00 PM: Registration and exhibits (booths from various
vendors)
6:00 PM - 6:10 PM: Introductions
6:10 PM - 6:40 PM: The state of FPGA Validation & Debugging
6:40 - 7:30: Eric Bogatin How the board will screw up your beautiful
transceiver signals, and what you can do about it
7:30 PM- 8:20 PM: A brief talks from the vendors about their debug
tools and solutions & Vendor Talk
8:20 PM - 8:30 PM: TBD (By Mentor Graphics)
8:30 PM- 9:00 PM: Networking and exhibits (booths from various
vendors)
Registration: FREE! Feel free to bring a friend. Please fill the form
below to RSVP using the form at
http://www.fpgacentral.com/fpgacamp/silicon-valley-ca-usa/debugging-your-fpga-11-nov-2009-silicon-
or at Linkedin event url - http://events.linkedin.com/FPGACamp-Debugging-FPGA/pub/136177
Contact us if you would like to:
* Volunteer with us
* Speak or Refer a speaker
* If you are a vendor
- Would like to put a booth - Free
- Demo/Talk about a product (Tell us what and why)- Free (
http://www.fpgacentral.com/fpgacamp/guideline )
- Buy audience some food / drinks
- Give away eval boards, books, kits or goodies to attendees
More details visit: http://www.fpgacentral.com/fpgacamp
the design phase and the debug and
verification phase. The primary tasks in the design phase are entry,
simulation, and implementation. The primary tasks in the Debug and
Verification phase are to validate the design and correct any bugs
found.
The recent advancements in FPGA densities have changed the way we
think of design & debug of a FPGA. This camp will focus on what can
you do as an engineer to make debugging your FPGA a science rather
then an art. It will also introduce to you various tools that you can
use to shorten the debug cycle.
Agenda: Tentative
5:00 PM- 6:00 PM: Registration and exhibits (booths from various
vendors)
6:00 PM - 6:10 PM: Introductions
6:10 PM - 6:40 PM: The state of FPGA Validation & Debugging
6:40 - 7:30: Eric Bogatin How the board will screw up your beautiful
transceiver signals, and what you can do about it
7:30 PM- 8:20 PM: A brief talks from the vendors about their debug
tools and solutions & Vendor Talk
8:20 PM - 8:30 PM: TBD (By Mentor Graphics)
8:30 PM- 9:00 PM: Networking and exhibits (booths from various
vendors)
Registration: FREE! Feel free to bring a friend. Please fill the form
below to RSVP using the form at
http://www.fpgacentral.com/fpgacamp/silicon-valley-ca-usa/debugging-your-fpga-11-nov-2009-silicon-
or at Linkedin event url - http://events.linkedin.com/FPGACamp-Debugging-FPGA/pub/136177
Contact us if you would like to:
* Volunteer with us
* Speak or Refer a speaker
* If you are a vendor
- Would like to put a booth - Free
- Demo/Talk about a product (Tell us what and why)- Free (
http://www.fpgacentral.com/fpgacamp/guideline )
- Buy audience some food / drinks
- Give away eval boards, books, kits or goodies to attendees
More details visit: http://www.fpgacentral.com/fpgacamp