Announcing release of OSVVM 2013.04

Discussion in 'VHDL' started by Jim Lewis, May 1, 2013.

  1. Jim Lewis

    Jim Lewis Guest

    OSVVM release 2013.04 is now available at either or

    Open Source VHDL Verification Methodology (OSVVM) is VHDL’s leading edge verification methodology. OSVVM makes adding functional coverage, randomization, and Intelligent Coverage (coverage driven randomization) to your VHDL testbench simple, concise, and powerful.

    With OSVVM, you don't need a specialized verification language such as SystemVerilog or 'e' to do verification, in fact, in many key areas, OSVVM is astep ahead.

    You can get more information about OSVVM at or at

    Get training in our VHDL Testbenches and Verification - OS-VVM Boot Camp. See
    Jim Lewis, May 1, 2013
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.

Share This Page