Another strage timing problem

Discussion in 'VHDL' started by Kload, Oct 23, 2003.

  1. Kload

    Kload Guest

    Hi again,

    Following up on my earlier post, I have come across another unusual
    timing problem. It seems I have timing paths that pass through flip
    flops. I've attached an example from the timing report. Using FPGA
    Editor to examine the implementation I have been able to confirm that
    oath addrRange<1> and addrRange<2> are flip flop outputs. In both cases
    the inputs seems to come through the carry logic, though and XOR gate,
    through a multiplexer to the D input of the flip flop.

    Thanks in advance for your help.

    --------------------------------------------------------------------------------
    Slack: -2.537ns path ROBAVGSEG2/endAddr<8> to
    ROBAVGSEG2/dataSum<16> relative to
    20.000ns delay constraint

    Path ROBAVGSEG2/endAddr<8> to ROBAVGSEG2/dataSum<16> contains 10 levels
    of logic:
    Path starting from Comp: CLB_R22C54.S0.CLK (from CLK180)
    To Delay type Delay(ns) Physical Resource
    Logical Resource(s)
    ------------------------------------------------- --------
    CLB_R22C54.S0.YQ Tcko 1.372R ROBAVGSE/eAddr<8>
    ROBAVGSE/eAddr_reg<8>
    CLB_R21C58.S1.F1 net (fanout=6) 2.258R ROBAVGSE/eAddr<8>
    CLB_R21C58.S1.X Tilo 0.738R ROBAVGSE/syn6957
    ROBAVGSE/C2679
    CLB_R25C58.S1.G3 net (fanout=1) 1.633R ROBAVGSE/syn6957
    CLB_R25C58.S1.Y Tilo 0.738R ROBAVGSE/C1432
    ROBAVGSE/C2677
    CLB_R25C58.S1.F3 net (fanout=2) 0.130R ROBAVGSE/syn6963
    CLB_R25C58.S1.X Tilo 0.738R ROBAVGSE/C1432
    ROBAVGSE/C2676
    CLB_R23C55.S1.F4 net (fanout=16) 1.975R ROBAVGSE/C1432
    CLB_R23C55.S1.X Tilo 0.738R ROBAVGSE/C1291/N21
    ROBAVGSE/C2663
    CLB_R24C59.S1.F1 net (fanout=1) 1.871R ROBAVGSE/C1291/N21
    CLB_R24C59.S1.COUT Topcyf 1.445R ROBAVGSE/addrRange<1>
    ROBAVGSE/C1281/C4/C0
    ROBAVGSE/C1281/C4/C2
    ROBAVGSE/C1281/C5/C2
    CLB_R23C59.S1.CIN net (fanout=1) 0.000R ROBAVGSE/C1281/C5/C2/O
    CLB_R23C59.S1.Y Tciny 0.590R ROBAVGSE/addrRange<2>
    ROBAVGSE/C1281/C6/C2
    ROBAVGSE/C1281/C7/C1
    CLB_R25C60.S1.F2 net (fanout=6) 1.577R ROBAVGSE/N7566
    CLB_R25C60.S1.X Tilo 0.738R ROBAVGSE/syn2456
    ROBAVGS2/C2558
    CLB_R26C67.S0.G2 net (fanout=7) 1.766R ROBAVGSE/syn2456
    CLB_R26C67.S0.Y Tilo 0.738R ROBAVGSE/C92/N85
    ROBAVGSE/C2458
    CLB_R21C75.S1.CE net (fanout=9) 2.544R ROBAVGSE/C92/N85
    CLB_R21C75.S1.CLK Tceck 0.948R ROBAVGSE/dSum<16>
    ROBAVGSE/dSum_reg<16>
    -------------------------------------------------
    Total (8.783ns logic, 13.754ns route) 22.537ns (to CLK180)
    (39.0% logic, 61.0% route)
    Kload, Oct 23, 2003
    #1
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  2. Kload

    John_H Guest

    Greetings, Kload.

    The timing report that you see does not show your flops driving NET
    elements, but their inclusion in the timing report is misleading for
    new engineers. The Xilinx devices work with "slices" which are
    treated as a single element within the tools to some degree. Each
    slice can contain many smaller parts such as LUTs, registers, MUXCY
    elements, XORCYs, MUXF5s, and so on. The first name in one "group"
    from the CLB timing element (such as Tilo or Topcyf) corresponds to
    the name the Xilinx tool gave to the entire slice. If you have the
    regular XIlinx tools (rather than just Webpack) you can use the FPGA
    Editor to look at the place & route implementation inside the device.
    If you find the ROBAVGSE/addrRange<1> COMPonent and open it up to view
    the innerds of that slice, you'll see the register you were worried
    about as well as the other piece-parts that make up that slice to
    include the named elements:
    ROBAVGSE/C1281/C4/C0
    ROBAVGSE/C1281/C4/C2
    ROBAVGSE/C1281/C5/C2
    Which actually *are* part of your carry chain.

    The "net" items are the actual signals that propagate out of the
    slice. Your flop isn't part of the carry chain logic, but is packed
    in the same slice as that change, affecting performance very little.

    Your difficulties with this timing path include not-so-great delay
    paths for the rather large amount of logic. If you can figure out how
    to reduce the levels of logic (number of LUTs passed through as
    indicated by the Tilo times) or can get the slices to pack closer
    together with floorplanning, RLOCed macros, or better placement
    methods (each is a slightly advanced design aspect) you should get
    better times. I've kept the "rule of thumb" that a 50% logic / 50%
    route is a "good" mix and longer routes can be cut down toward that
    50/50 mix. Your numbers show on the bottom of your report item as
    "(39.0% logic, 61.0% route)".

    Enjoy the journey.
    - John_H


    Kload <> wrote in message news:<bn7r0c$peu$>...
    > Hi again,
    >
    > Following up on my earlier post, I have come across another unusual
    > timing problem. It seems I have timing paths that pass through flip
    > flops. I've attached an example from the timing report. Using FPGA
    > Editor to examine the implementation I have been able to confirm that
    > oath addrRange<1> and addrRange<2> are flip flop outputs. In both cases
    > the inputs seems to come through the carry logic, though and XOR gate,
    > through a multiplexer to the D input of the flip flop.
    >
    > Thanks in advance for your help.
    >
    > --------------------------------------------------------------------------------
    > Slack: -2.537ns path ROBAVGSEG2/endAddr<8> to
    > ROBAVGSEG2/dataSum<16> relative to
    > 20.000ns delay constraint
    >
    > Path ROBAVGSEG2/endAddr<8> to ROBAVGSEG2/dataSum<16> contains 10 levels
    > of logic:
    > Path starting from Comp: CLB_R22C54.S0.CLK (from CLK180)
    > To Delay type Delay(ns) Physical Resource
    > Logical Resource(s)
    > ------------------------------------------------- --------
    > CLB_R22C54.S0.YQ Tcko 1.372R ROBAVGSE/eAddr<8>
    > ROBAVGSE/eAddr_reg<8>
    > CLB_R21C58.S1.F1 net (fanout=6) 2.258R ROBAVGSE/eAddr<8>
    > CLB_R21C58.S1.X Tilo 0.738R ROBAVGSE/syn6957
    > ROBAVGSE/C2679
    > CLB_R25C58.S1.G3 net (fanout=1) 1.633R ROBAVGSE/syn6957
    > CLB_R25C58.S1.Y Tilo 0.738R ROBAVGSE/C1432
    > ROBAVGSE/C2677
    > CLB_R25C58.S1.F3 net (fanout=2) 0.130R ROBAVGSE/syn6963
    > CLB_R25C58.S1.X Tilo 0.738R ROBAVGSE/C1432
    > ROBAVGSE/C2676
    > CLB_R23C55.S1.F4 net (fanout=16) 1.975R ROBAVGSE/C1432
    > CLB_R23C55.S1.X Tilo 0.738R ROBAVGSE/C1291/N21
    > ROBAVGSE/C2663
    > CLB_R24C59.S1.F1 net (fanout=1) 1.871R ROBAVGSE/C1291/N21
    > CLB_R24C59.S1.COUT Topcyf 1.445R ROBAVGSE/addrRange<1>
    > ROBAVGSE/C1281/C4/C0
    > ROBAVGSE/C1281/C4/C2
    > ROBAVGSE/C1281/C5/C2
    > CLB_R23C59.S1.CIN net (fanout=1) 0.000R ROBAVGSE/C1281/C5/C2/O
    > CLB_R23C59.S1.Y Tciny 0.590R ROBAVGSE/addrRange<2>
    > ROBAVGSE/C1281/C6/C2
    > ROBAVGSE/C1281/C7/C1
    > CLB_R25C60.S1.F2 net (fanout=6) 1.577R ROBAVGSE/N7566
    > CLB_R25C60.S1.X Tilo 0.738R ROBAVGSE/syn2456
    > ROBAVGS2/C2558
    > CLB_R26C67.S0.G2 net (fanout=7) 1.766R ROBAVGSE/syn2456
    > CLB_R26C67.S0.Y Tilo 0.738R ROBAVGSE/C92/N85
    > ROBAVGSE/C2458
    > CLB_R21C75.S1.CE net (fanout=9) 2.544R ROBAVGSE/C92/N85
    > CLB_R21C75.S1.CLK Tceck 0.948R ROBAVGSE/dSum<16>
    > ROBAVGSE/dSum_reg<16>
    > -------------------------------------------------
    > Total (8.783ns logic, 13.754ns route) 22.537ns (to CLK180)
    > (39.0% logic, 61.0% route)
    John_H, Oct 23, 2003
    #2
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